Inventor
VAN DYKE JAMES M
US45 patents
⚠️ This page may combine multiple inventors who share the name “VAN DYKE JAMES M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
NVIDIA CORP
33 patentsUS7805587B1Sep 28, 2010
Memory addressing controlled by PTE fields
NVIDIA CORP440 citations99
US6853382B1Feb 8, 2005
Controller for a memory system having multiple partitions
NVIDIA CORP114 citations99
US6825847B1Nov 30, 2004
System and method for real-time compression of pixel colors
NVIDIA CORP156 citations99
US6734861B1May 11, 2004
System, method and article of manufacture for an interlock module in a computer graphics processing pipeline
NVIDIA CORP160 citations99
US7340577B1Mar 4, 2008
Method and system for efficiently executing reads after writes in a memory employing delayed write data
NVIDIA CORP65 citations98
US7080194B1Jul 18, 2006
Method and system for memory access arbitration for minimizing read/write turnaround penalties
NVIDIA CORP64 citations98
US6894689B1May 17, 2005
Occlusion culling method and apparatus for graphics systems
NVIDIA CORP115 citations98
US6646639B1Nov 11, 2003
Modified method and apparatus for improved occlusion culling in graphics systems
NVIDIA CORP196 citations98
US6961057B1Nov 1, 2005
Method and apparatus for managing and accessing depth data in a computer graphics system
NVIDIA CORP114 citations97
US7068272B1Jun 27, 2006
System, method and article of manufacture for Z-value and stencil culling prior to rendering in a computer graphics processing pipeline
NVIDIA CORP129 citations96
US7932912B1Apr 26, 2011
Frame buffer tag addressing for partitioned graphics memory supporting non-power of two number of memory elements
NVIDIA CORP34 citations93
US7872657B1Jan 18, 2011
Memory addressing scheme using partition strides
NVIDIA CORP42 citations93
US7286134B1Oct 23, 2007
System and method for packing data in a tiled graphics memory
NVIDIA CORP25 citations93
US6999088B1Feb 14, 2006
Memory system having multiple subpartitions
NVIDIA CORP36 citations93
US6829689B1Dec 7, 2004
Method and system for memory access arbitration for minimizing read/write turnaround penalties
NVIDIA CORP23 citations93
US7596647B1Sep 29, 2009
Urgency based arbiter
NVIDIA CORP26 citations92
US7525551B1Apr 28, 2009
Anisotropic texture prefiltering
NVIDIA CORP20 citations92
US6647456B1Nov 11, 2003
High bandwidth-low latency memory controller
NVIDIA CORP42 citations91
US10909033B1Feb 2, 2021
Techniques for efficiently partitioning memory
NVIDIA CORP14 citations86
US9424201B2Aug 23, 2016
Migrating pages of different sizes between heterogeneous processors
NVIDIA CORP10 citations84
US7884829B1Feb 8, 2011
Partitioned graphics memory supporting non-power of two number of memory elements
NVIDIA CORP16 citations84
US7882292B1Feb 1, 2011
Urgency based arbiter
NVIDIA CORP8 citations84
US7680992B1Mar 16, 2010
Read-modify-write memory with low latency for critical requests
NVIDIA CORP14 citations84
US7617368B2Nov 10, 2009
Memory interface with independent arbitration of precharge, activate, and read/write
NVIDIA CORP17 citations84
US7808507B1Oct 5, 2010
Compression tag state interlock
NVIDIA CORP8 citations83
US7400327B1Jul 15, 2008
Apparatus, system, and method for a partitioned memory
NVIDIA CORP5 citations74
US9798487B2Oct 24, 2017
Migrating pages of different sizes between heterogeneous processors
NVIDIA CORP3 citations73
US7603503B1Oct 13, 2009
Efficiency based arbiter
NVIDIA CORP7 citations73
US6957298B1Oct 18, 2005
System and method for a high bandwidth-low latency memory controller
NVIDIA CORP7 citations72
US7369133B1May 6, 2008
Apparatus, system, and method for a partitioned memory for a graphics system
NVIDIA CORP3 citations63
US11429534B2Aug 30, 2022
Addressing cache slices in a last level cache
NVIDIA CORP0 citations57
US10983919B2Apr 20, 2021
Addressing cache slices in a last level cache
NVIDIA CORP0 citations57
US9690715B2Jun 27, 2017
Selecting hash values based on matrix rank
NVIDIA CORP0 citations42
VAN DYKE JAMES M
8 patentsUS8072463B1Dec 6, 2011
Graphics system with virtual memory pages and non-power of two number of memory elements
VAN DYKE JAMES M108 citations98
US8775112B2Jul 8, 2014
System and method for increasing die yield
VAN DYKE JAMES M17 citations92
US8872833B2Oct 28, 2014
Integrated circuit configuration system and method
VAN DYKE JAMES M9 citations84
US8698814B1Apr 15, 2014
Programmable compute engine screen mapping
VAN DYKE JAMES M10 citations84
US8700865B1Apr 15, 2014
Compressed data access system and method
VAN DYKE JAMES M15 citations83
US8441495B1May 14, 2013
Compression tag state interlock
VAN DYKE JAMES M6 citations83
US8139073B1Mar 20, 2012
Early compression tag lookup for memory accesses
VAN DYKE JAMES M13 citations83
US9348751B2May 24, 2016
System and methods for distributing a power-of-two virtual memory page across a non-power-of two number of DRAM partitions
VAN DYKE JAMES M3 citations73