Inventor
CHITLUR NAGABHUSHAN
US16 patents
⚠️ This page may combine multiple inventors who share the name “CHITLUR NAGABHUSHAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
13 patentsUS12204441B2Jan 21, 2025
Flushing cache lines involving persistent memory
INTEL CORP2 citations72
US11194753B2Dec 7, 2021
Platform interface layer and protocol for accelerators
INTEL CORP4 citations72
US9639372B2May 2, 2017
Apparatus and method for heterogeneous processors mapping to virtual cores
INTEL CORP2 citations72
US9329900B2May 3, 2016
Hetergeneous processor apparatus and method
INTEL CORP6 citations72
US11251576B2Feb 15, 2022
Circuit card with coherent interconnect
INTEL CORP2 citations61
US7617363B2Nov 10, 2009
Low latency message passing mechanism
INTEL CORP5 citations59
US12112204B2Oct 8, 2024
Modular accelerator function unit (AFU) design, discovery, and reuse
INTEL CORP0 citations58
US11416300B2Aug 16, 2022
Modular accelerator function unit (AFU) design, discovery, and reuse
INTEL CORP1 citations58
US11372787B2Jun 28, 2022
Unified address space for multiple links
INTEL CORP0 citations58
US10929134B2Feb 23, 2021
Execution unit accelerator
INTEL CORP0 citations54
US12450008B2Oct 21, 2025
Remote storage for hardware microservices hosted on XPUs and SOC-XPU platforms
INTEL CORP0 citations50
US11809899B2Nov 7, 2023
Methods and apparatus for accelerating virtual machine migration
INTEL CORP0 citations45
US7930459B2Apr 19, 2011
Coherent input output device
INTEL CORP0 citations37
STILLWELL JR PAUL M
2 patentsUS8082418B2Dec 20, 2011
Method and apparatus for coherent device initialization and access
STILLWELL JR PAUL M10 citations78
US8473715B2Jun 25, 2013
Dynamic accelerator reconfiguration via compiler-inserted initialization message and configuration address and size information
STILLWELL JR PAUL M2 citations57