Inventor
STEINER IAN M
US30 patents
⚠️ This page may combine multiple inventors who share the name “STEINER IAN M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
26 patentsUS11922220B2Mar 5, 2024
Function as a service (FaaS) system enhancements
INTEL CORP44 citations92
US11169560B2Nov 9, 2021
Configuration of base clock frequency of processor based on usage parameters
INTEL CORP6 citations83
US9880601B2Jan 30, 2018
Method and apparatus to control a link power state
INTEL CORP5 citations83
US9495001B2Nov 15, 2016
Forcing core low power states in a processor
INTEL CORP6 citations82
US10372197B2Aug 6, 2019
User level control of power management policies
INTEL CORP3 citations73
US12066853B2Aug 20, 2024
Configuration of base clock frequency of processor based on usage parameters
INTEL CORP2 citations72
US11703906B2Jul 18, 2023
Configuration of base clock frequency of processor based on usage parameters
INTEL CORP3 citations72
US10048744B2Aug 14, 2018
Apparatus and method for thermal management in a multi-chip package
INTEL CORP2 citations72
US9141426B2Sep 22, 2015
Processor having per core and package level P0 determination functionality
INTEL CORP6 citations70
US11409560B2Aug 9, 2022
System, apparatus and method for power license control of a processor
INTEL CORP5 citations69
US12416940B2Sep 16, 2025
Configuration of base clock frequency of processor based on usage parameters
INTEL CORP0 citations62
US11403194B2Aug 2, 2022
Systems and methods for in-field core failover
INTEL CORP1 citations62
US10552270B2Feb 4, 2020
Systems and methods for in-field core failover
INTEL CORP1 citations62
US9535487B2Jan 3, 2017
User level control of power management policies
INTEL CORP1 citations62
US9170624B2Oct 27, 2015
User level control of power management policies
INTEL CORP3 citations62
US7885914B2Feb 8, 2011
Systems, methods and apparatuses for rank coordination
INTEL CORP2 citations62
US11194373B2Dec 7, 2021
Hybrid prioritized resource allocation in thermally-or power-constrained computing devices
INTEL CORP0 citations61
US10627885B2Apr 21, 2020
Hybrid prioritized resource allocation in thermally- or power-constrained computing devices
INTEL CORP1 citations61
US10310588B2Jun 4, 2019
Forcing core low power states in a processor
INTEL CORP1 citations61
US7991963B2Aug 2, 2011
In-memory, in-page directory cache coherency scheme
INTEL CORP4 citations61
US11726910B2Aug 15, 2023
Dynamic control of memory bandwidth allocation for a processor
INTEL CORP1 citations58
US10509455B2Dec 17, 2019
Method and apparatus to control a link power state
INTEL CORP0 citations51
US9405351B2Aug 2, 2016
Performing frequency coordination in a multiprocessor system
INTEL CORP0 citations51
US9760409B2Sep 12, 2017
Dynamically modifying a power/performance tradeoff based on a processor utilization
INTEL CORP0 citations49
US10146287B2Dec 4, 2018
Processor power monitoring and control with dynamic load balancing
INTEL CORP0 citations40
US9501299B2Nov 22, 2016
Minimizing performance loss on workloads that exhibit frequent core wake-up activity
INTEL CORP0 citations39