Inventor · disambiguated record
Gordon Raymond Chiu
Also filed as: CHIU GORDON · CHIU GORDON R · CHIU GORDON RAYMOND
62 granted patents·1 pending application·396 citations·filing 2005–2020
98Inventor score
Top patents by PatentIndex Score
63 records- 0194US7500216B1Method and apparatus for performing physical synthesis hill-climbing on multi-processor machinesALTERA CORP·Filed 2007·Granted Mar 3, 2009·42 cites·27 claims
- 0293US8918748B1M/A for performing automatic latency optimization on system designs for implementation on programmable hardwareCHIU GORDON RAYMOND·Filed 2012·Granted Dec 23, 2014·21 cites·20 claims
- 0393US8499201B1Methods and systems for measuring and presenting performance data of a memory controller systemCHIU GORDON RAYMOND·Filed 2010·Granted Jul 30, 2013·25 cites·25 claims
- 0491US9529952B1Speculative circuit design component graphical user interfaceALTERA CORP·Filed 2015·Granted Dec 27, 2016·8 cites·19 claims
- 0591US9098662B1Configuring a device to debug systems in real-timeALTERA CORP·Filed 2013·Granted Aug 4, 2015·17 cites·22 claims
- 0691US8897083B1Memory interface circuitry with data strobe signal sharing capabilitiesALTERA CORP·Filed 2012·Granted Nov 25, 2014·15 cites·19 claims
- 0790US10614354B2Method and apparatus for implementing layers on a convolutional neural network acceleratorALTERA CORP·Filed 2016·Granted Apr 7, 2020·11 cites·20 claims
- 0890US8296696B1Method and apparatus for performing simultaneous register retiming and combinational resynthesis during physical synthesisCHIU GORDON RAYMOND·Filed 2008·Granted Oct 23, 2012·24 cites·21 claims
- 0989US9117022B1Hierarchical arbitrationCHIU GORDON RAYMOND·Filed 2012·Granted Aug 25, 2015·15 cites·22 claims
- 1088US10726328B2Method and apparatus for designing and implementing a convolution neural net acceleratorALTERA CORP·Filed 2015·Granted Jul 28, 2020·10 cites·19 claims
- 1188US9330218B1Integrated circuits having input-output circuits with dedicated memory controller circuitryALTERA CORP·Filed 2014·Granted May 3, 2016·11 cites·18 claims
- 1288US9292638B1Method and apparatus for performing timing closure analysis when performing register retimingALTERA CORP·Filed 2014·Granted Mar 22, 2016·10 cites·19 claims
- 1387US10387603B2Incremental register retiming of an integrated circuit designALTERA CORP·Filed 2018·Granted Aug 20, 2019·5 cites·17 claims
- 1487US9679633B2Circuits and methods for DQS autogatingALTERA CORP·Filed 2016·Granted Jun 13, 2017·8 cites·20 claims
- 1586US9971858B1Method and apparatus for performing register retiming in the presence of false path timing analysis exceptionsALTERA CORP·Filed 2015·Granted May 15, 2018·5 cites·22 claims
- 1686US9275184B1Method and apparatus for performing timing closure analysis when performing register retimingALTERA CORP·Filed 2014·Granted Mar 1, 2016·8 cites·20 claims
- 1786US8929162B1Gating and sampling a data strobe signal using a shared enable signalFENDER JOSHUA DAVID·Filed 2012·Granted Jan 6, 2015·10 cites·18 claims
- 1885US10909296B2Method and apparatus for relocating design modules while preserving timing closureALTERA CORP·Filed 2019·Granted Feb 2, 2021·3 cites·20 claims
- 1985US9996652B2Incremental register retiming of an integrated circuit designALTERA CORP·Filed 2015·Granted Jun 12, 2018·5 cites·13 claims
- 2085US9529947B1Register retiming and verification of an integrated circuit designALTERA CORP·Filed 2014·Granted Dec 27, 2016·8 cites·23 claims
- 2185US8977998B1Timing analysis with end-of-life pessimism removalALTERA CORP·Filed 2013·Granted Mar 10, 2015·12 cites·21 claims
- 2285US7996797B1Method and apparatus for performing multiple stage physical synthesisALTERA CORP·Filed 2007·Granted Aug 9, 2011·10 cites·32 claims
- 2384US8856702B1Method and apparatus for performing multiple stage physical synthesisALTERA CORP·Filed 2013·Granted Oct 7, 2014·5 cites·21 claims
- 2484US8510688B1Method and apparatus for performing multiple stage physical synthesisSINGH DESHANAND·Filed 2011·Granted Aug 13, 2013·6 cites·19 claims
- 2583US10339244B1Method and apparatus for implementing user-guided speculative register retiming in a compilation flowALTERA CORP·Filed 2015·Granted Jul 2, 2019·4 cites·19 claims
- 2683US9710591B1Method and apparatus for performing register retiming in the presence of timing analysis exceptionsALTERA CORP·Filed 2015·Granted Jul 18, 2017·4 cites·24 claims
- 2783US9323538B1Systems and methods for memory interface calibrationBLUNNO IVAN·Filed 2012·Granted Apr 26, 2016·11 cites·23 claims
- 2883US9257164B2Circuits and methods for DQS autogatingALTERA CORP·Filed 2013·Granted Feb 9, 2016·7 cites·23 claims
- 2979US8813018B1Method and apparatus for automatically configuring memory sizeGAMSA BENJAMIN·Filed 2012·Granted Aug 19, 2014·8 cites·17 claims
- 3078US10963777B2Method and apparatus for implementing layers on a convolutional neural network acceleratorALTERA CORP·Filed 2020·Granted Mar 30, 2021·1 cites·20 claims
- 3178US10339238B2Method and apparatus for performing register retiming in the presence of timing analysis exceptionsALTERA CORP·Filed 2017·Granted Jul 2, 2019·2 cites·24 claims
- 3278US8977810B2Systems and methods for using memory commandsCHIU GORDON RAYMOND·Filed 2012·Granted Mar 10, 2015·7 cites·23 claims
- 3377US9058436B1Method and system for reducing the effect of component agingALTERA CORP·Filed 2012·Granted Jun 16, 2015·4 cites·19 claims
- 3476US9733855B1System and methods for adjusting memory command placementALTERA CORP·Filed 2013·Granted Aug 15, 2017·5 cites·21 claims
- 3576US8201114B1Method and apparatus for performing look up table unpacking and repacking for resynthesisMANOHARARAJAH VALAVAN·Filed 2009·Granted Jun 12, 2012·7 cites·30 claims
- 3676US7620925B1Method and apparatus for performing post-placement routability optimizationALTERA CORP·Filed 2006·Granted Nov 17, 2009·7 cites·16 claims
- 3775US10224908B1Low frequency variation calibration circuitryFENDER JOSHUA DAVID·Filed 2011·Granted Mar 5, 2019·4 cites·8 claims
- 3875US8929152B1Retiming programmable devices incorporating random access memoriesALTERA CORP·Filed 2014·Granted Jan 6, 2015·4 cites·20 claims
- 3972US9195793B1Method and apparatus for relocating design modules while preserving timing closureALTERA CORP·Filed 2014·Granted Nov 24, 2015·2 cites·24 claims
- 4071US7444613B1Systems and methods for mapping arbitrary logic functions into synchronous embedded memoriesALTERA CORP·Filed 2006·Granted Oct 28, 2008·4 cites·38 claims
- 4171US7412677B1Detecting reducible registersALTERA CORP·Filed 2006·Granted Aug 12, 2008·5 cites·30 claims
- 4269US9489480B1Techniques for compiling and generating a performance analysis for an integrated circuit designALTERA CORP·Filed 2014·Granted Nov 8, 2016·2 cites·18 claims
- 4369US9251876B1Retiming programmable devices incorporating random access memoriesALTERA CORP·Filed 2014·Granted Feb 2, 2016·2 cites·20 claims
- 4468US9229888B1Area-efficient dynamically-configurable memory controllerCHIU GORDON RAYMOND·Filed 2012·Granted Jan 5, 2016·2 cites·15 claims
- 4568US9047215B1Method and system for reducing the effect of component recoveryALTERA CORP·Filed 2012·Granted Jun 2, 2015·2 cites·21 claims
- 4666US9552456B2Methods and apparatus for probing signals from a circuit after register retimingALTERA CORP·Filed 2015·Granted Jan 24, 2017·1 cites·25 claims
- 4764US7797666B1Systems and methods for mapping arbitrary logic functions into synchronous embedded memoriesALTERA CORP·Filed 2008·Granted Sep 14, 2010·2 cites·20 claims
- 4863US9698795B1Supporting pseudo open drain input/output standards in a programmable logic deviceALTERA CORP·Filed 2013·Granted Jul 4, 2017·1 cites·19 claims
- 4961US10394997B2Method and apparatus for relocating design modules while preserving timing closureALTERA CORP·Filed 2018·Granted Aug 27, 2019·0 cites·22 claims
- 5061US9384311B1Programmable device configuration methods incorporating retimingALTERA CORP·Filed 2014·Granted Jul 5, 2016·1 cites·20 claims
Showing the top 50 of 63 patent records by PatentIndex Score.
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