Inventor
GUILFORD JAMES D
US140 patents
⚠️ This page may combine multiple inventors who share the name “GUILFORD JAMES D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
38 patentsUS9859918B1Jan 2, 2018
Technologies for performing speculative decompression
INTEL CORP41 citations99
US10268412B2Apr 23, 2019
Technologies for deterministic constant-time data compression
INTEL CORP17 citations98
US10263637B2Apr 16, 2019
Technologies for performing speculative decompression
INTEL CORP14 citations98
US10191684B2Jan 29, 2019
Technologies for flexibly compressing and decompressing data
INTEL CORP20 citations98
US10042639B2Aug 7, 2018
Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction
INTEL CORP39 citations98
US9484954B1Nov 1, 2016
Methods and apparatus to parallelize data decompression
INTEL CORP48 citations98
US6671827B2Dec 30, 2003
Journaling for parallel hardware threads in multithreaded processor
INTEL CORP75 citations98
US10116327B2Oct 30, 2018
Technologies for efficiently compressing data with multiple hash tables
INTEL CORP14 citations96
US10033404B2Jul 24, 2018
Technologies for efficiently compressing data with run detection
INTEL CORP15 citations96
US9973207B2May 15, 2018
Technologies for heuristic huffman code generation
INTEL CORP14 citations96
US9954552B2Apr 24, 2018
Technologies for performing low-latency decompression with tree caching
INTEL CORP16 citations96
US9929747B2Mar 27, 2018
Technologies for high-performance single-stream LZ77 compression
INTEL CORP14 citations96
US10135463B1Nov 20, 2018
Method and apparatus for accelerating canonical huffman encoding
INTEL CORP20 citations94
US10128868B1Nov 13, 2018
Efficient dictionary for lossless compression
INTEL CORP20 citations94
US9584155B1Feb 28, 2017
Look-ahead hash chain matching for data compression
INTEL CORP21 citations94
US7020871B2Mar 28, 2006
Breakpoint method for parallel hardware threads in multithreaded processor
INTEL CORP62 citations94
US9929748B1Mar 27, 2018
Techniques for data compression verification
INTEL CORP16 citations93
US9419648B1Aug 16, 2016
Supporting data compression using match scoring
INTEL CORP18 citations93
US6944850B2Sep 13, 2005
Hop method for stepping parallel hardware threads
INTEL CORP39 citations91
US10310897B2Jun 4, 2019
Hardware accelerators and methods for offload operations
INTEL CORP14 citations85
US10635338B2Apr 28, 2020
Technologies for a high-ratio compression accelerator with heterogeneous history buffers
INTEL CORP2 citations84
US10230392B2Mar 12, 2019
Techniques for parallel data decompression
INTEL CORP9 citations84
US9940131B2Apr 10, 2018
Rotate instructions that complete execution either without writing or reading flags
INTEL CORP4 citations84
US9940130B2Apr 10, 2018
Rotate instructions that complete execution either without writing or reading flags
INTEL CORP4 citations84
US9916160B2Mar 13, 2018
Rotate instructions that complete execution either without writing or reading flags
INTEL CORP4 citations84
US9917597B1Mar 13, 2018
Method and apparatus for accelerated data compression with hints and filtering
INTEL CORP9 citations84
US9876509B2Jan 23, 2018
Methods and apparatus to parallelize data decompression
INTEL CORP4 citations84
US9853660B1Dec 26, 2017
Techniques for parallel data compression
INTEL CORP15 citations84
US9825648B1Nov 21, 2017
Method and apparatus for hybrid compression processing for high levels of compression
INTEL CORP14 citations84
US9825647B1Nov 21, 2017
Method and apparatus for decompression acceleration in multi-cycle decoder based platforms
INTEL CORP11 citations84
US9768802B2Sep 19, 2017
Look-ahead hash chain matching for data compression
INTEL CORP8 citations84
US9537504B1Jan 3, 2017
Heterogeneous compression architecture for optimized compression ratio
INTEL CORP8 citations84
US9495166B2Nov 15, 2016
Method and apparatus for performing a shift and exclusive or operation in a single instruction
INTEL CORP4 citations84
US9419647B2Aug 16, 2016
Partitioned data compression using accelerator
INTEL CORP7 citations84
US9251377B2Feb 2, 2016
Instructions processors, methods, and systems to process secure hash algorithms
INTEL CORP3 citations84
US9027104B2May 5, 2015
Instructions processors, methods, and systems to process secure hash algorithms
INTEL CORP9 citations84
US7337275B2Feb 26, 2008
Free list and ring data structure management
INTEL CORP18 citations84
US6684395B2Jan 27, 2004
Multiple image dynamic bind and load procedure for a multi-processor
INTEL CORP15 citations83
GOPAL VINODH
9 patentsUS9960917B2May 1, 2018
Matrix multiply accumulate instruction
GOPAL VINODH39 citations94
US9235414B2Jan 12, 2016
SIMD integer multiply-accumulate instruction for multi-precision arithmetic
GOPAL VINODH53 citations94
US9747105B2Aug 29, 2017
Method and apparatus for performing a shift and exclusive or operation in a single instruction
GOPAL VINODH11 citations91
US9740484B2Aug 22, 2017
Processor-based apparatus and method for processing bit streams using bit-oriented instructions through byte-oriented storage
GOPAL VINODH8 citations84
US9473168B1Oct 18, 2016
Systems, methods, and apparatuses for compression using hardware and software
GOPAL VINODH14 citations84
US9292297B2Mar 22, 2016
Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction
GOPAL VINODH7 citations84
US8947270B2Feb 3, 2015
Apparatus and method to accelerate compression and decompression operations
GOPAL VINODH8 citations84
US8914641B2Dec 16, 2014
Method for signing and verifying data using multiple hash algorithms and digests in PKCS
GOPAL VINODH16 citations84
US8549264B2Oct 1, 2013
Add instructions to add three source operands
GOPAL VINODH6 citations84
YAP KIRK S
2 patentsWOLRICH GILBERT M
1 patentShowing the top 50 of 140 patents by PatentIndex Score.