Inventor · disambiguated record
Joseph P. Gergen
Also filed as: GERGEN JOSEPH · GERGEN JOSEPH P · GERGEN JOSEPH PAUL
17 granted patents·2 pending applications·267 citations·filing 1986–2025
93Inventor score
Files withMOTOROLA INC6FREESCALE SEMICONDUCTOR INC5NXP USA INC3BHAGAVATHEESWARAN GAYATHRI A1HOLT JAMES C1
Top patents by PatentIndex Score
19 records- 0185US4766561AMethod and apparatus for implementing multiple filters with shared componentsMOTOROLA INC·Filed 1986·Granted Aug 23, 1988·35 cites·7 claims
- 0276US5303355APipelined data processor which conditionally executes a predetermined looping instruction in hardwareMOTOROLA INC·Filed 1991·Granted Apr 12, 1994·74 cites·16 claims
- 0375US4785411ACascade filter structure with time overlapped partial addition operations and programmable tap lengthMOTOROLA INC·Filed 1986·Granted Nov 15, 1988·24 cites·8 claims
- 0473US9900390B2Method and apparatus for controlling wake events in a data processing systemFREESCALE SEMICONDUCTOR INC·Filed 2015·Granted Feb 20, 2018·2 cites·17 claims
- 0568US5442576AMultibit shifting apparatus, data processor using same, and method thereforMOTOROLA INC·Filed 1994·Granted Aug 15, 1995·52 cites·20 claims
- 0665US6751759B1Method and apparatus for pipeline hazard detectionFREESCALE SEMICONDUCTOR INC·Filed 2000·Granted Jun 15, 2004·14 cites·48 claims
- 0764US7107489B2Method and apparatus for debugging a data processing systemFREESCALE SEMICONDUCTOR INC·Filed 2002·Granted Sep 12, 2006·13 cites·16 claims
- 0863US8509370B2Phase locked loop device and method thereofBHAGAVATHEESWARAN GAYATHRI A·Filed 2009·Granted Aug 13, 2013·3 cites·20 claims
- 0963US7013409B2Method and apparatus for debugging a data processing systemFREESCALE SEMICONDUCTOR INC·Filed 2002·Granted Mar 14, 2006·12 cites·13 claims
- 1062US2025383682A1Overclocking detection and responseNXP BV·Filed 2025·Application pending·0 cites
- 1161US6842895B2Single instruction for multiple loopsFREESCALE SEMICONDUCTOR INC·Filed 2000·Granted Jan 11, 2005·10 cites·21 claims
- 1250US12175283B2Hardware-accelerated computing systemNXP USA INC·Filed 2021·Granted Dec 24, 2024·0 cites·15 claims
- 1347US10817413B2Hardware-based memory management for system-on-chip (SoC) integrated circuits that identify blocks of continuous available tokens needed to store dataNXP USA INC·Filed 2018·Granted Oct 27, 2020·0 cites·20 claims
- 1446US9207979B1Explicit barrier scheduling mechanism for pipelining of stream processing algorithmsHOLT JAMES C·Filed 2014·Granted Dec 8, 2015·0 cites·19 claims
- 1544US5001665AAddressing technique for providing read, modify and write operations in a single data processing cycle with serpentine configured RAMsMOTOROLA INC·Filed 1986·Granted Mar 19, 1991·13 cites·5 claims
- 1642US8700878B2Event triggered memory mapped accessSCHWARZ WILLIAM D·Filed 2009·Granted Apr 15, 2014·0 cites·12 claims
- 1740US11861403B2Method and system for accelerator thread managementNXP USA INC·Filed 2020·Granted Jan 2, 2024·0 cites·20 claims
- 1837US2004019828A1Method and apparatus for debugging a data processing systemFiled 2002·Application pending·0 cites
- 1936US5363322AData processor with an integer multiplication function on a fractional multiplierMOTOROLA INC·Filed 1991·Granted Nov 8, 1994·15 cites·19 claims
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