Inventor
DATTA SUMAN
US191 patents
Patents
50 patentsUS7825437B2Nov 2, 2010
Unity beta ratio tri-gate transistor static random access memory (SRAM)
INTEL CORP166 citations99
US7518196B2Apr 14, 2009
Field effect transistor with narrow bandgap source and drain regions and method of fabrication
INTEL CORP72 citations99
US7358121B2Apr 15, 2008
Tri-gate devices and methods of fabrication
INTEL CORP153 citations99
US7348284B2Mar 25, 2008
Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
INTEL CORP141 citations99
US7268058B2Sep 11, 2007
Tri-gate transistors and methods to fabricate same
INTEL CORP164 citations99
US7241653B2Jul 10, 2007
Nonplanar device with stress incorporation layer and method of fabrication
INTEL CORP125 citations99
US7170120B2Jan 30, 2007
Carbon nanotube energy well (CNEW) field effect transistor
INTEL CORP149 citations99
US7126199B2Oct 24, 2006
Multilayer metal gate electrode
INTEL CORP154 citations99
US7005366B2Feb 28, 2006
Tri-gate devices and methods of fabrication
INTEL CORP121 citations99
US6974738B2Dec 13, 2005
Nonplanar device with stress incorporation layer and method of fabrication
INTEL CORP97 citations99
US6914295B2Jul 5, 2005
Tri-gate devices and methods of fabrication
INTEL CORP71 citations99
US6909151B2Jun 21, 2005
Nonplanar device with stress incorporation layer and method of fabrication
INTEL CORP241 citations99
US6858478B2Feb 22, 2005
Tri-gate devices and methods of fabrication
INTEL CORP629 citations99
US7898041B2Mar 1, 2011
Block contact architectures for nanoscale channel transistors
INTEL CORP113 citations98
US7569443B2Aug 4, 2009
Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate
INTEL CORP72 citations98
US7547637B2Jun 16, 2009
Methods for patterning a semiconductor film
INTEL CORP52 citations98
US7531393B2May 12, 2009
Non-planar MOS structure with a strained channel region
INTEL CORP121 citations98
US7525160B2Apr 28, 2009
Multigate device with recessed strain regions
INTEL CORP65 citations98
US7494862B2Feb 24, 2009
Methods for uniform doping of non-planar transistor structures
INTEL CORP70 citations98
US7485503B2Feb 3, 2009
Dielectric interface for group III-V semiconductor device
INTEL CORP63 citations98
US7479421B2Jan 20, 2009
Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
INTEL CORP105 citations98
US7456476B2Nov 25, 2008
Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
INTEL CORP222 citations98
US7456068B2Nov 25, 2008
Forming ultra-shallow junctions
INTEL CORP66 citations98
US7449373B2Nov 11, 2008
Method of ion implanting for tri-gate devices
INTEL CORP74 citations98
US7407847B2Aug 5, 2008
Stacked multi-gate transistor design and method of fabrication
INTEL CORP99 citations98
US7390709B2Jun 24, 2008
Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
INTEL CORP71 citations98
US7381608B2Jun 3, 2008
Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode
INTEL CORP85 citations98
US7279375B2Oct 9, 2007
Block contact architectures for nanoscale channel transistors
INTEL CORP93 citations98
US7220635B2May 22, 2007
Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer
INTEL CORP78 citations98
US7193279B2Mar 20, 2007
Non-planar MOS structure with a strained channel region
INTEL CORP76 citations98
US7157378B2Jan 2, 2007
Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
INTEL CORP107 citations98
US7153784B2Dec 26, 2006
Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
INTEL CORP86 citations98
US7153734B2Dec 26, 2006
CMOS device with metal and silicide gate electrodes and a method for making it
INTEL CORP64 citations98
US7148548B2Dec 12, 2006
Semiconductor device with a high-k gate dielectric and a metal gate electrode
INTEL CORP117 citations98
US7064066B1Jun 20, 2006
Method for making a semiconductor device having a high-k gate dielectric and a titanium carbide gate electrode
INTEL CORP65 citations98
US6970373B2Nov 29, 2005
Method and apparatus for improving stability of a 6T CMOS SRAM cell
INTEL CORP84 citations98
US7820513B2Oct 26, 2010
Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
INTEL CORP81 citations97
US7569869B2Aug 4, 2009
Transistor having tensile strained channel and system including same
INTEL CORP59 citations97
US7074680B2Jul 11, 2006
Method for making a semiconductor device having a high-k gate dielectric
INTEL CORP64 citations97
US7893506B2Feb 22, 2011
Field effect transistor with narrow bandgap source and drain regions and method of fabrication
INTEL CORP35 citations96
US7858481B2Dec 28, 2010
Method for fabricating transistor with thinned channel
INTEL CORP28 citations96
US7560756B2Jul 14, 2009
Tri-gate devices and methods of fabrication
INTEL CORP31 citations96
US7514346B2Apr 7, 2009
Tri-gate devices and methods of fabrication
INTEL CORP28 citations96
US7504678B2Mar 17, 2009
Tri-gate devices and methods of fabrication
INTEL CORP35 citations96
US7427794B2Sep 23, 2008
Tri-gate devices and methods of fabrication
INTEL CORP39 citations96
US7355281B2Apr 8, 2008
Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrode
INTEL CORP47 citations96
US7323423B2Jan 29, 2008
Forming high-k dielectric layers on smooth substrates
INTEL CORP49 citations96
US7223679B2May 29, 2007
Transistor gate electrode having conductor material layer
INTEL CORP34 citations96
US7176090B2Feb 13, 2007
Method for making a semiconductor device that includes a metal gate electrode
INTEL CORP58 citations96
US7138323B2Nov 21, 2006
Planarizing a semiconductor structure to form replacement metal gates
INTEL CORP51 citations96
Showing the top 50 of 191 patents by PatentIndex Score.