Inventor · disambiguated record
Ali S. El-Zein
Also filed as: EL-ZEIN ALI · EL-ZEIN ALI S
18 granted patents·5 pending applications·44 citations·filing 2005–2023
90Inventor score
Top patents by PatentIndex Score
23 records- 0193US11663381B2Clock mapping in an integrated circuit designIBM·Filed 2021·Granted May 30, 2023·4 cites·24 claims
- 0277US8640065B2Circuit verification using computational algebraic geometryJANSSEN GRADUS GEERT·Filed 2012·Granted Jan 28, 2014·7 cites·22 claims
- 0376US7284210B2Method for reconfiguration of random biases in a synthesized design without recompilationIBM·Filed 2005·Granted Oct 16, 2007·8 cites·20 claims
- 0473US8443314B1Abstraction level-preserving conversion of flip-flop-inferred hardware description language (HDL) to instantiated HDLEL-ZEIN ALI S·Filed 2012·Granted May 14, 2013·4 cites·21 claims
- 0571US8230406B2Compiler option consistency checking during incremental hardware design language compilationCARBONE RICHARD L H·Filed 2006·Granted Jul 24, 2012·10 cites·16 claims
- 0666US8234604B2Co-optimization of embedded systems utilizing symbolic executionEL-ZEIN ALI S·Filed 2008·Granted Jul 31, 2012·5 cites·20 claims
- 0765US8141048B2Sequential encoding for relational analysis (SERA) of a software modelBAUMGARTNER JASON R·Filed 2007·Granted Mar 20, 2012·3 cites·21 claims
- 0861US7823097B2Unrolling hardware design generate statements in a source window debuggerIBM·Filed 2006·Granted Oct 26, 2010·2 cites·18 claims
- 0955US2025124202A1Verifying multi-cycle interconnect synthesis optimization in automatically generated physical hierarchy chip designIBM·Filed 2023·Application pending·0 cites
- 1053US10599804B1Pin cloning and subway creation on automatically generated design physical hierarchyIBM·Filed 2018·Granted Mar 24, 2020·0 cites·20 claims
- 1153US10565338B2Equivalency verification for hierarchical referencesIBM·Filed 2017·Granted Feb 18, 2020·0 cites·17 claims
- 1253US8713494B2Synthesizing VHDL multiple wait FSMS into RT level FSMS by preprocessingIBM·Filed 2013·Granted Apr 29, 2014·0 cites·9 claims
- 1353US8140313B2Techniques for modeling variables in subprograms of hardware description language programsDRASNY GABOR·Filed 2008·Granted Mar 20, 2012·1 cites·12 claims
- 1449US9495496B2Non-invasive insertion of logic functions into a register-transfer level (‘RTL’) designIBM·Filed 2014·Granted Nov 15, 2016·0 cites·18 claims
- 1549US2025124201A1Automatic clock-gating insertion in register-transfer level designIBM·Filed 2023·Application pending·0 cites
- 1647US12050852B2Signal pre-routing in an integrated circuit designIBM·Filed 2021·Granted Jul 30, 2024·0 cites·20 claims
- 1747US2023072735A1Refinement of an integrated circuit designIBM·Filed 2021·Application pending·0 cites
- 1845US12204832B2Logical clock connection in an integrated circuit designIBM·Filed 2021·Granted Jan 21, 2025·0 cites·22 claims
- 1945US8495533B2Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs by preprocessingDRASNY GABOR·Filed 2006·Granted Jul 23, 2013·0 cites·17 claims
- 2045US8439784B2Braking systemEL-ZEIN ALI·Filed 2008·Granted May 14, 2013·0 cites·14 claims
- 2145US2024152676A1Early power estimation on a derived physical hierarchy in chip designIBM·Filed 2022·Application pending·0 cites
- 2244US2023074528A1Iterative design of an integrated circuit designIBM·Filed 2021·Application pending·0 cites
- 2342US7506287B2Method, system, and program product for pre-compile processing of hardware design language (HDL) source filesIBM·Filed 2006·Granted Mar 17, 2009·0 cites·20 claims
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