Inventor · disambiguated record
Michael Scott Mcilvaine
Also filed as: MCILVAINE MICHAEL S · MCILVAINE MICHAEL SCOTT
54 granted patents·22 pending applications·180 citations·filing 2003–2023
97Inventor score
Files withQUALCOMM INC39MICROSOFT TECHNOLOGY LICENSING LLC24IBM4BURDA GREGORY CHRISTOPHER1DEBRUYNE LESLIE MARK1
Top patents by PatentIndex Score
76 records- 0191US8578117B2Write-through-read (WTR) comparator circuits, systems, and methods use of same with a multiple-port fileBURDA GREGORY CHRISTOPHER·Filed 2010·Granted Nov 5, 2013·37 cites·22 claims
- 0290US7624256B2System and method wherein conditional instructions unconditionally provide outputQUALCOMM INC·Filed 2005·Granted Nov 24, 2009·24 cites·15 claims
- 0389US7152155B2System and method of correcting a branch mispredictionQUALCOMM INC·Filed 2005·Granted Dec 19, 2006·19 cites·17 claims
- 0487US7624254B2Segmented pipeline flushing for mispredicted branchesQUALCOMM INC·Filed 2007·Granted Nov 24, 2009·18 cites·1 claims
- 0586US7587580B2Power efficient instruction prefetch mechanismQUALCOMM INC·Filed 2005·Granted Sep 8, 2009·14 cites·11 claims
- 0682US11068273B2Swapping and restoring context-specific branch predictor states on context switches in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Jul 20, 2021·3 cites·21 claims
- 0782US9477478B2Multi level indirect predictor using confidence counter and program counter address filter schemeKOTHARI KULIN N·Filed 2012·Granted Oct 25, 2016·10 cites·17 claims
- 0877US11074077B1Reusing executed, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-executionMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Jul 27, 2021·1 cites·35 claims
- 0972US7210024B2Conditional instruction execution via emissary instruction for condition evaluationQUALCOMM INC·Filed 2005·Granted Apr 24, 2007·5 cites·19 claims
- 1071US12229568B2Methods and circuitry for efficient management of local branch history registersMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2023·Granted Feb 18, 2025·0 cites·20 claims
- 1171US7669039B2Use of register renaming system for forwarding intermediate results between constituent instructions of an expanded instructionQUALCOMM INC·Filed 2007·Granted Feb 23, 2010·5 cites·19 claims
- 1270US10956162B2Operand-based reach explicit dataflow processors, and related methods and computer-readable mediaMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Mar 23, 2021·1 cites·30 claims
- 1370US9477476B2Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable mediaQUALCOMM INC·Filed 2012·Granted Oct 25, 2016·3 cites·25 claims
- 1469US7698536B2Method and system for providing an energy efficient register fileQUALCOMM INC·Filed 2005·Granted Apr 13, 2010·4 cites·21 claims
- 1569US7366877B2Speculative instruction issue in a simultaneously multithreaded processorIBM·Filed 2003·Granted Apr 29, 2008·12 cites·14 claims
- 1667US11768688B1Methods and circuitry for efficient management of local branch history registersMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Sep 26, 2023·0 cites·20 claims
- 1767US10474462B2Dynamic pipeline throttling using confidence-based weighting of in-flight branch instructionsQUALCOMM INC·Filed 2016·Granted Nov 12, 2019·1 cites·30 claims
- 1865US11842196B2Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructionsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted Dec 12, 2023·0 cites·23 claims
- 1965US11726787B2Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetchingMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Aug 15, 2023·0 cites·23 claims
- 2063US8661229B2Power efficient instruction prefetch mechanismSARTORIUS THOMAS ANDREW·Filed 2009·Granted Feb 25, 2014·2 cites·20 claims
- 2162US11188334B2Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructionsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Nov 30, 2021·0 cites·17 claims
- 2262US9710269B2Early conditional selection of an operandDIEFFENDERFER JAMES NORRIS·Filed 2006·Granted Jul 18, 2017·2 cites·28 claims
- 2361US7949861B2Method and apparatus for managing instruction flushing in a microprocessor's instruction pipelineQUALCOMM INC·Filed 2005·Granted May 24, 2011·2 cites·23 claims
- 2461US7263577B2Power saving methods and apparatus to selectively enable comparators in a CAM renaming register file based on known processor stateQUALCOMM INC·Filed 2005·Granted Aug 28, 2007·2 cites·20 claims
- 2560US12260220B2Accelerating fetch target queue (FTQ) processing in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Mar 25, 2025·0 cites·20 claims
- 2660US9460018B2Method and apparatus for tracking extra data permissions in an instruction cacheDEBRUYNE LESLIE MARK·Filed 2012·Granted Oct 4, 2016·2 cites·26 claims
- 2760US9411590B2Method to improve speed of executing return branch instructions in a processorQUALCOMM INC·Filed 2013·Granted Aug 9, 2016·1 cites·5 claims
- 2860US9195466B2Fusing conditional write instructions having opposite conditions in instruction processing circuits, and related processor systems, methods, and computer-readable mediaQUALCOMM INC·Filed 2012·Granted Nov 24, 2015·1 cites·25 claims
- 2959US11360773B2Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetchingMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Jun 14, 2022·0 cites·23 claims
- 3059US7681022B2Efficient interrupt return address save mechanismQUALCOMM INC·Filed 2006·Granted Mar 16, 2010·1 cites·22 claims
- 3157US11928474B2Selectively updating branch predictors for loops executed from loop buffers in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Mar 12, 2024·0 cites·20 claims
- 3257US7793079B2Method and system for expanding a conditional instruction into a unconditional instruction and a select instructionQUALCOMM INC·Filed 2007·Granted Sep 7, 2010·2 cites·21 claims
- 3356US11126437B2Load instruction with final read indicator field to invalidate a buffer or cache entry storing the memory address holding load dataMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Sep 21, 2021·0 cites·18 claims
- 3456US7093100B2Translation look aside buffer (TLB) with increased translational capacity for multi-threaded computer processesIBM·Filed 2003·Granted Aug 15, 2006·5 cites·17 claims
- 3555US11487545B2Processor branch prediction circuit employing back-invalidation of prediction cache entries based on decoded branch instructions and related methodsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted Nov 1, 2022·0 cites·20 claims
- 3654US11915002B2Providing extended branch target buffer (BTB) entries for storing trunk branch metadata and leaf branch metadataMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Feb 27, 2024·0 cites·16 claims
- 3753US11175926B2Providing exception stack management using stack panic fault exceptions in processor-based devicesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Nov 16, 2021·0 cites·20 claims
- 3853US10108419B2Dependency-prediction of instructionsQUALCOMM INC·Filed 2014·Granted Oct 23, 2018·0 cites·30 claims
- 3953US7725684B2Speculative instruction issue in a simultaneously multithreaded processorIBM·Filed 2008·Granted May 25, 2010·0 cites·13 claims
- 4052US11789740B2Performing branch predictor training using probabilistic counter updates in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted Oct 17, 2023·0 cites·15 claims
- 4151US8127114B2System and method for executing instructions prior to an execution stage in a processorSETH KIRAN RAVI·Filed 2007·Granted Feb 28, 2012·1 cites·16 claims
- 4249US10838731B2Branch prediction based on load-path historyQUALCOMM INC·Filed 2018·Granted Nov 17, 2020·0 cites·33 claims
- 4349US9823929B2Optimizing performance for context-dependent instructionsQUALCOMM INC·Filed 2013·Granted Nov 21, 2017·0 cites·32 claims
- 4449US9317293B2Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable mediaQUALCOMM INC·Filed 2013·Granted Apr 19, 2016·0 cites·28 claims
- 4549US9146741B2Eliminating redundant masking operations instruction processing circuits, and related processor systems, methods, and computer-readable mediaQUALCOMM INC·Filed 2012·Granted Sep 29, 2015·0 cites·20 claims
- 4649US2024201998A1Performing storage-free instruction cache hit prediction in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Application pending·0 cites
- 4748US10318436B2Precise invalidation of virtually tagged cachesQUALCOMM INC·Filed 2017·Granted Jun 11, 2019·0 cites·30 claims
- 4848US9858077B2Issuing instructions to execution pipelines based on register-associated preferences, and related instruction processing circuits, processor systems, methods, and computer-readable mediaQUALCOMM INC·Filed 2013·Granted Jan 2, 2018·0 cites·22 claims
- 4948US2024168885A1Providing location-based prefetching in processor-based devicesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Application pending·0 cites
- 5047US9471325B2Method and apparatus for selective renaming in a microprocessorQUALCOMM INC·Filed 2013·Granted Oct 18, 2016·0 cites·30 claims
Showing the top 50 of 76 patent records by PatentIndex Score.
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