Inventor · disambiguated record
Hunt Hang Jiang
Also filed as: JIANG HUNT · JIANG HUNT H · JIANG HUNT HANG
29 granted patents·13 pending applications·643 citations·filing 1998–2025
97Inventor score
Files withMONOLITHIC POWER SYSTEMS INC13CHENGDU MONOLITHIC POWER SYS10FUJITSU LTD9JIANG HUNT HANG3YANG ERIC2
Top patents by PatentIndex Score
42 records- 0195US6054761AMulti-layer circuit substrates and electrical assemblies having conductive composition connectorsFUJITSU LTD·Filed 1998·Granted Apr 25, 2000·103 cites·38 claims
- 0294US8461669B2Integrated power converter package with die stackingYANG ERIC·Filed 2010·Granted Jun 11, 2013·22 cites·22 claims
- 0393US8604597B2Multi-die packages incorporating flip chip dies and associated packaging methodsJIANG HUNT HANG·Filed 2011·Granted Dec 10, 2013·22 cites·19 claims
- 0493US6869750B2Structure and method for forming a multilayered structureFUJITSU LTD·Filed 2002·Granted Mar 22, 2005·62 cites·64 claims
- 0593US6326555B1Method and structure of z-connected laminated substrate for high density electronic packagingFUJITSU LTD·Filed 1999·Granted Dec 4, 2001·93 cites·44 claims
- 0692US6163957AMultilayer laminated substrates with high density interconnects and methods of making the sameFUJITSU LTD·Filed 1998·Granted Dec 26, 2000·138 cites·19 claims
- 0788US6271107B1Semiconductor with polymeric layerFUJITSU LTD·Filed 1999·Granted Aug 7, 2001·95 cites·33 claims
- 0887US8283758B2Microelectronic packages with enhanced heat dissipation and methods of manufacturingJIANG HUNT HANG·Filed 2010·Granted Oct 9, 2012·10 cites·7 claims
- 0987US7944048B2Chip scale package for power devices and method for making the sameMONOLITHIC POWER SYSTEMS INC·Filed 2007·Granted May 17, 2011·15 cites·21 claims
- 1084US8064202B2Sandwich structure with double-sided cooling and EMI shieldingYIN JIAN·Filed 2010·Granted Nov 22, 2011·8 cites·15 claims
- 1183US10461052B2Copper structures with intermetallic coating for integrated circuit chipsMONOLITHIC POWER SYSTEMS INC·Filed 2017·Granted Oct 29, 2019·3 cites·14 claims
- 1281US9754909B2Copper structures with intermetallic coating for integrated circuit chipsMONOLITHIC POWER SYSTEMS INC·Filed 2015·Granted Sep 5, 2017·3 cites·8 claims
- 1381US8361899B2Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturingMONOLITHIC POWER SYSTEMS INC·Filed 2010·Granted Jan 29, 2013·4 cites·11 claims
- 1481US7513037B2Method of embedding components in multi-layer circuit boardsFUJITSU LTD·Filed 2005·Granted Apr 7, 2009·9 cites·11 claims
- 1579US9070671B2Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturingMONOLITHIC POWER SYSTEMS INC·Filed 2014·Granted Jun 30, 2015·3 cites·15 claims
- 1679US8906797B2Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturingMONOLITHIC POWER SYSTEMS INC·Filed 2012·Granted Dec 9, 2014·3 cites·12 claims
- 1775US6428942B1Multilayer circuit structure build up methodFUJITSU LTD·Filed 1999·Granted Aug 6, 2002·32 cites·63 claims
- 1869US8810013B2Integrated power converter package with die stackingYANG ERIC·Filed 2013·Granted Aug 19, 2014·2 cites·12 claims
- 1965US12266583B2Flip chip package unit and associated packaging methodCHENGDU MONOLITHIC POWER SYS·Filed 2022·Granted Apr 1, 2025·0 cites·12 claims
- 2065US7999364B2Method and flip chip structure for power devicesMONOLITHIC POWER SYSTEMS INC·Filed 2007·Granted Aug 16, 2011·3 cites·10 claims
- 2164US2025246445A1Flip chip package unit and associated packaging methodCHENGDU MONOLITHIC POWER SYS·Filed 2025·Application pending·0 cites
- 2263US10083930B2Semiconductor device reducing parasitic loop inductance of systemMONOLITHIC POWER SYSTEMS INC·Filed 2017·Granted Sep 25, 2018·1 cites·13 claims
- 2361US6579474B2Conductive compositionFUJITSU LTD·Filed 2001·Granted Jun 17, 2003·6 cites·20 claims
- 2460US12002787B2Multi-die package structure and multi-die co-packing methodCHENGDU MONOLITHIC POWER SYS·Filed 2021·Granted Jun 4, 2024·0 cites·12 claims
- 2558US11652029B23-D package structure for isolated power module and the method thereofMONOLITHIC POWER SYSTEMS INC·Filed 2021·Granted May 16, 2023·0 cites·15 claims
- 2655US2025096209A1Double-side-cooling power moduleMONOLITHIC POWER SYSTEMS INC·Filed 2023·Application pending·0 cites
- 2752US2015155226A1Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturingMONOLITHIC POWER SYSTEMS INC·Filed 2015·Application pending·0 cites
- 2851US12159792B2Flip chip package unit comprising thermal protection film and associated packaging methodCHENGDU MONOLITHIC POWER SYS·Filed 2022·Granted Dec 3, 2024·0 cites·6 claims
- 2950US11670600B2Panel level metal wall grids array for integrated circuit packagingCHENGDU MONOLITHIC POWER SYS·Filed 2021·Granted Jun 6, 2023·0 cites·11 claims
- 3050US11616017B2Integrated circuit package structure, integrated circuit package unit and associated packaging methodCHENGDU MONOLITHIC POWER SYS·Filed 2021·Granted Mar 28, 2023·0 cites·20 claims
- 3149US11824001B2Integrated circuit package structure and integrated circuit package unitCHENGDU MONOLITHIC POWER SYS·Filed 2021·Granted Nov 21, 2023·0 cites·17 claims
- 3248US2022208732A1Multi-die co-packed module and multi-die co-packing methodCHENGDU MONOLITHIC POWER SYS·Filed 2021·Application pending·0 cites
- 3348US2022199581A1Multi-die package structure and multi-die co-packing methodCHENGDU MONOLITHIC POWER SYS·Filed 2021·Application pending·0 cites
- 3447US2022208714A1Integrated circuit package structure, integrated circuit package unit and associated packaging methodCHENGDU MONOLITHIC POWER SYS·Filed 2021·Application pending·0 cites
- 3546US2022230991A1Multi-die package structure and multi-die co-packing methodMONOLITHIC POWER SYSTEMS INC·Filed 2021·Application pending·0 cites
- 3645US2009108443A1Flip-Chip Interconnect StructureMONOLITHIC POWER SYSTEMS INC·Filed 2007·Application pending·0 cites
- 3741US2010252918A1Multi-die package with improved heat dissipationJIANG HUNT H·Filed 2009·Application pending·0 cites
- 3840US6281040B1Methods for making circuit substrates and electrical assembliesFUJITSU LTD·Filed 1999·Granted Aug 28, 2001·6 cites·89 claims
- 3939US2002119396A1Structure and method for forming z-laminated multilayered packaging substrateFiled 2001·Application pending·0 cites
- 4038US2002175402A1Structure and method of embedding components in multi-layer substratesFiled 2001·Application pending·0 cites
- 4137US2012193772A1Stacked die packages with flip-chip and wire bonding diesJIANG HUNT HANG·Filed 2011·Application pending·0 cites
- 4235US2002151164A1Structure and method for depositing solder bumps on a waferFiled 2001·Application pending·0 cites
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