Inventor

OBERMAN STUART F

US61 patents

⚠️ This page may combine multiple inventors who share the name “OBERMAN STUART F”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OBERMAN STUART F

ADVANCED MICRO DEVICES INC

Shared FP and SIMD 3D multiplier

Early completion of iterative division

Method and apparatus for performing multiple types of multiplication including signed and unsigned multiplication

Rapid execution of FCMOV following FCOMI by storing comparison result in temporary register in floating point unit

Method and apparatus for achieving higher frequencies of exactly rounded results

Floating point addition pipeline configured to perform floating point-to-integer and integer-to-floating point conversion operations

Floating point addition pipeline including extreme value, comparison and accumulate functions

Method and apparatus for rapid execution of FCOM and FSTSW

Optimized allocation of multi-pipeline executable and specific pipeline executable instructions to execution pipelines based on criteria

Multi-function bipartite look-up table

Bipartite look-up table with output values having minimized absolute error

Floating point arithmetic unit including an efficient close data path

Leading one prediction unit for normalizing close path subtraction results within a floating point arithmetic unit

Microprocessor including an efficient implemention of an accumulate instruction

Method and apparatus for denormal load handling

Method and apparatus for compressing intermediate products

Method and apparatus for calculating reciprocals and reciprocal square roots

Method and apparatus for simultaneously performing arithmetic on two or more pairs of operands

Method and apparatus for performing vector and scalar multiplication and calculating rounded products

Apparatus and method for handling tiny numbers using a super sticky bit in a microprocessor

Close path selection unit for performing effective subtraction within a floating point arithmetic unit

Efficient method for performing close path subtraction in a floating point arithmetic unit

Floating point addition pipeline including extreme value, comparison and accumulate functions

NVIDIA CORP

Single interconnect providing read and write access to a memory shared by concurrent threads

Execution of parallel groups of threads with per-instruction serialization

Multipurpose functional unit with multiply-add and format conversion pipeline

Tracking register usage during multithreaded processing using a scoreboard having separate memory regions and storing sequential register size indicators

Multipurpose functional unit with single-precision and double-precision operations

Multipurpose arithmetic functional unit

Multi-purpose floating point and integer multiply-add functional unit with multiplication-comparison test addition and exponent pipelines

Operand collector architecture

Method and apparatus to ensure consistency of depth values computed in different sections of a graphics processor

Executing an SIMD instruction requiring P operations on an execution unit that performs Q operations at a time (Q&lt;P)

Computing anisotropic texture mapping parameters

High-speed function approximation

Programmable graphics processor for multithreaded execution of programs

Multipurpose functional unit with multiplication pipeline, addition pipeline, addition pipeline and logical test pipeline capable of performing integer multiply-add operations

NISHAN SYSTEMS INC

Method and apparatus for scheduling packet flow on a fibre channel arbitrated loop

Dynamic selection of lowest latency path in a network switch

Method and system for managing time division multiplexing (TDM) timeslots in a network switch

Packet input thresholding for resource distribution in a network switch

COON BRETT W

Shared memory with parallel access and access conflict resolution mechanism

Scoreboard having size indicators for tracking sequential destination register usage in a multi-threaded processor

Shared single-access memory with management of multiple parallel requests

LINDHOLM JOHN ERIK

Programmable graphics processor for multithreaded execution of programs

Programmable graphics processor for multithreaded execution of programs

JUFFA NORBERT

Graphics processor with memory management unit and cache coherent link

OBERMAN STUART F

Multipurpose arithmetic functional unit

BROCADE COMM SYSTEMS INC

High jitter scheduling of interleaved frames in an arbitrated loop

MILLS PETER C

Dynamic load balancing of instructions for execution by heterogeneous processing engines

Executing an SIMD instruction requiring P operations on an execution unit that performs Q operations at a time (Q<P)