Inventor · disambiguated record
David Shippy
Also filed as: SHIPPY DAVID · SHIPPY DAVID J · SHIPPY DAVID JAMES
52 granted patents·7 pending applications·1,252 citations·filing 1988–2023
99Inventor score
Files withIBM48ALTERA CORP3ADVANCED MICRO DEVICES INC2TEXAS INSTRUMENTS INC2ABERNATHY CHRISTOPHER M1
Top patents by PatentIndex Score
59 records- 0192US7350056B2Method and apparatus for issuing instructions from an issue queue in an information handling systemIBM·Filed 2005·Granted Mar 25, 2008·32 cites·17 claims
- 0290US7401242B2Dynamic power management in a processor designIBM·Filed 2005·Granted Jul 15, 2008·22 cites·7 claims
- 0389US6820143B2On-chip data transfer in multi-processor systemIBM·Filed 2002·Granted Nov 16, 2004·58 cites·24 claims
- 0488US4943984AData processing system parallel data bus having a single oscillator clocking apparatusIBM·Filed 1988·Granted Jul 24, 1990·99 cites·22 claims
- 0587US7313673B2Fine grained multi-thread dispatch block mechanismIBM·Filed 2005·Granted Dec 25, 2007·18 cites·20 claims
- 0685US7490224B2Time-of-life counter design for handling instruction flushes from a queueIBM·Filed 2005·Granted Feb 10, 2009·13 cites·3 claims
- 0783US6981072B2Memory management in multiprocessor systemIBM·Filed 2003·Granted Dec 27, 2005·34 cites·24 claims
- 0882US7681056B2Dynamic power management in a processor designIBM·Filed 2008·Granted Mar 16, 2010·10 cites·7 claims
- 0982US4953081ALeast recently used arbiter with programmable high priority mode and performance monitorIBM·Filed 1988·Granted Aug 28, 1990·81 cites·9 claims
- 1078US7093080B2Method and apparatus for coherent memory structure of heterogeneous processor systemsIBM·Filed 2003·Granted Aug 15, 2006·25 cites·20 claims
- 1178US6957305B2Data streaming mechanism in a microprocessorIBM·Filed 2002·Granted Oct 18, 2005·24 cites·7 claims
- 1278US6237081B1Queuing method and apparatus for facilitating the rejection of sequential instructions in a processorIBM·Filed 1998·Granted May 22, 2001·81 cites·20 claims
- 1377US7461239B2Apparatus and method for handling data cache misses out-of-order for asynchronous pipelinesIBM·Filed 2006·Granted Dec 2, 2008·7 cites·23 claims
- 1477US6336183B1System and method for executing store instructionsIBM·Filed 1999·Granted Jan 1, 2002·71 cites·16 claims
- 1576US7900024B2Handling data cache misses out-of-order for asynchronous pipelinesIBM·Filed 2008·Granted Mar 1, 2011·6 cites·12 claims
- 1676US6226722B1Integrated level two cache and controller with multiple ports, L1 bypass and concurrent accessingIBM·Filed 1994·Granted May 1, 2001·77 cites·20 claims
- 1775US10095647B2Accelerator architecture on a programmable platformALTERA CORP·Filed 2015·Granted Oct 9, 2018·2 cites·27 claims
- 1875US7103748B2Memory management for real-time applicationsIBM·Filed 2002·Granted Sep 5, 2006·21 cites·14 claims
- 1975US6061780AExecution unit chaining for single cycle extract instruction having one serial shift left and one serial shift right execution unitsTEXAS INSTRUMENTS INC·Filed 1998·Granted May 9, 2000·71 cites·2 claims
- 2074US9329666B2Power throttling queueADVANCED MICRO DEVICES INC·Filed 2012·Granted May 3, 2016·3 cites·20 claims
- 2174US8082423B2Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updatesABERNATHY CHRISTOPHER MICHAEL·Filed 2005·Granted Dec 20, 2011·7 cites·1 claims
- 2273US11797473B2Accelerator architecture on a programmable platformALTERA CORP·Filed 2018·Granted Oct 24, 2023·1 cites·24 claims
- 2372US5822758AMethod and system for high performance dynamic and user programmable cache arbitrationIBM·Filed 1996·Granted Oct 13, 1998·65 cites·43 claims
- 2471US6543002B1Recovery from hang condition in a microprocessorIBM·Filed 1999·Granted Apr 1, 2003·55 cites·25 claims
- 2571US5822755ADual usage memory selectively behaving as a victim cache for L1 cache or as a tag array for L2 cacheIBM·Filed 1996·Granted Oct 13, 1998·59 cites·12 claims
- 2670US7913070B2Time-of-life counter for handling instruction flushes from a queueIBM·Filed 2008·Granted Mar 22, 2011·4 cites·2 claims
- 2770US6349382B1System for store forwarding assigning load and store instructions to groups and reorder queues to keep track of program orderIBM·Filed 1999·Granted Feb 19, 2002·56 cites·9 claims
- 2870US2024078211A1Accelerator architecture on a programmable platformALTERA CORP·Filed 2023·Application pending·0 cites
- 2969US9164570B2Dynamic re-configuration for low power in a data processorADVANCED MICRO DEVICES INC·Filed 2012·Granted Oct 20, 2015·2 cites·21 claims
- 3068US7596682B2Architected register file system utilizes status and control registers to control read/write operations between threadsIBM·Filed 2004·Granted Sep 29, 2009·12 cites·15 claims
- 3167US7328330B2Queue design supporting dependency checking and issue for SIMD instructions within a general purpose processorIBM·Filed 2005·Granted Feb 5, 2008·3 cites·1 claims
- 3267US4961140AApparatus and method for extending a parallel synchronous data and message busIBM·Filed 1988·Granted Oct 2, 1990·38 cites·13 claims
- 3366US6336168B1System and method for merging multiple outstanding load miss instructionsIBM·Filed 1999·Granted Jan 1, 2002·46 cites·19 claims
- 3463US7769985B2Load address dependency mechanism system and method in a high frequency, low power processor systemIBM·Filed 2008·Granted Aug 3, 2010·2 cites·9 claims
- 3563US7370176B2System and method for high frequency stall designIBM·Filed 2005·Granted May 6, 2008·2 cites·6 claims
- 3662US7114035B2Software-controlled cache set management with software-generated class identifiersIBM·Filed 2003·Granted Sep 26, 2006·8 cites·19 claims
- 3757US7953960B2Method and apparatus for delaying a load miss flush until issuing the dependent instructionIBM·Filed 2005·Granted May 31, 2011·1 cites·21 claims
- 3857US7496776B2Power throttling method and apparatusIBM·Filed 2003·Granted Feb 24, 2009·4 cites·9 claims
- 3955US8051315B2Power throttling apparatusIBM·Filed 2008·Granted Nov 1, 2011·0 cites·13 claims
- 4055US6961820B2System and method for identifying and accessing streaming data in a locked portion of a cacheIBM·Filed 2003·Granted Nov 1, 2005·4 cites·23 claims
- 4154US5210828AMultiprocessing system with interprocessor communications facilityIBM·Filed 1990·Granted May 11, 1993·34 cites·4 claims
- 4252US7831808B2Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processorIBM·Filed 2007·Granted Nov 9, 2010·0 cites·12 claims
- 4352US2008148021A1High Frequency Stall DesignDEMENT JONATHAN JAMES·Filed 2008·Application pending·0 cites
- 4447US7363468B2Load address dependency mechanism system and method in a high frequency, low power processor systemIBM·Filed 2004·Granted Apr 22, 2008·1 cites·5 claims
- 4546US6298436B1Method and system for performing atomic memory accesses in a processor systemIBM·Filed 1999·Granted Oct 2, 2001·18 cites·11 claims
- 4646US4974147AProgrammable quiesce apparatus for retry, recovery and debugIBM·Filed 1988·Granted Nov 27, 1990·17 cites·5 claims
- 4745US6654876B1System for rejecting and reissuing instructions after a variable delay time periodIBM·Filed 1999·Granted Nov 25, 2003·16 cites·15 claims
- 4844US7484052B2Distributed address arbitration scheme for symmetrical multiprocessor systemIBM·Filed 2005·Granted Jan 27, 2009·0 cites·10 claims
- 4944US7120748B2Software-controlled cache set managementIBM·Filed 2003·Granted Oct 10, 2006·0 cites·21 claims
- 5044US7062612B2Updating remote locked cacheIBM·Filed 2002·Granted Jun 13, 2006·0 cites·16 claims
Showing the top 50 of 59 patent records by PatentIndex Score.
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