Inventor · disambiguated record
Andrew A. Bjorksten
Also filed as: BJORKSTEN ANDREW A · BJORKSTEN ANDREW AUGUSTUS
12 granted patents·240 citations·filing 1994–2006
92Inventor score
Top patents by PatentIndex Score
12 records- 0179US5896046ALatch structure for ripple domino logicIBM·Filed 1997·Granted Apr 20, 1999·32 cites·7 claims
- 0274US5930148AMethod and system for verifying a digital circuit design including dynamic circuit cells that utilize diverse circuit techniquesIBM·Filed 1996·Granted Jul 27, 1999·78 cites·23 claims
- 0367US5563818AMethod and system for performing floating-point division using selected approximation valuesIBM·Filed 1994·Granted Oct 8, 1996·56 cites·4 claims
- 0454US7080373B2Method and device for creating and using pre-internalized program filesFREESCALE SEMICONDUCTOR INC·Filed 2001·Granted Jul 18, 2006·6 cites·15 claims
- 0547US8099729B2Method and device for creating and using pre-internalized program filesPLAXTON IRIS M·Filed 2006·Granted Jan 17, 2012·1 cites·15 claims
- 0645US5764549AFast floating point result alignment apparatusIBM·Filed 1996·Granted Jun 9, 1998·18 cites·6 claims
- 0741US7221188B2Logic circuitryFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted May 22, 2007·2 cites·36 claims
- 0841US5771366AMethod and system for interchanging operands during complex instruction execution in a data processing systemIBM·Filed 1995·Granted Jun 23, 1998·15 cites·20 claims
- 0939US6018621AIdentifying an optimizable logic region in a logic networkIBM·Filed 1996·Granted Jan 25, 2000·11 cites·20 claims
- 1038US5903467ASelecting phase assignments for candidate nodes in a logic networkIBM·Filed 1996·Granted May 11, 1999·10 cites·16 claims
- 1134US6035110AIdentifying candidate nodes for phase assignment in a logic networkIBM·Filed 1996·Granted Mar 7, 2000·7 cites·8 claims
- 1230US5966522AMulti-phase clock distribution method and system for complex integrated-circuit devicesIBM·Filed 1997·Granted Oct 12, 1999·4 cites·6 claims
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