Inventor · disambiguated record
An Steegen
Also filed as: STEEGEN AN · STEEGEN AN L
26 granted patents·752 citations·filing 2003–2010
97Inventor score
Files withIBM26
Top patents by PatentIndex Score
26 records- 0198US6891192B2Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regionsIBM·Filed 2003·Granted May 10, 2005·179 cites·11 claims
- 0297US6921711B2Method for forming metal replacement gate of high performanceIBM·Filed 2003·Granted Jul 26, 2005·147 cites·25 claims
- 0395US7326610B2Process options of forming silicided metal gates for advanced CMOS devicesIBM·Filed 2005·Granted Feb 5, 2008·34 cites·13 claims
- 0494US7056794B2FET gate structure with metal gate electrode and silicide contactIBM·Filed 2004·Granted Jun 6, 2006·96 cites·20 claims
- 0592US7291528B2Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regionsIBM·Filed 2005·Granted Nov 6, 2007·16 cites·17 claims
- 0692US7067368B1Method for forming self-aligned dual salicide in CMOS technologiesIBM·Filed 2005·Granted Jun 27, 2006·17 cites·10 claims
- 0790US7029966B2Process options of forming silicided metal gates for advanced CMOS devicesIBM·Filed 2003·Granted Apr 18, 2006·53 cites·2 claims
- 0890US6869866B1Silicide proximity structures for CMOS device performance improvementsIBM·Filed 2003·Granted Mar 22, 2005·53 cites·23 claims
- 0989US7396714B2Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regionsIBM·Filed 2007·Granted Jul 8, 2008·11 cites·17 claims
- 1088US6936522B2Selective silicon-on-insulator isolation structure and methodIBM·Filed 2003·Granted Aug 30, 2005·37 cites·22 claims
- 1183US7056782B2CMOS silicide metal gate integrationIBM·Filed 2004·Granted Jun 6, 2006·25 cites·19 claims
- 1282US7326983B2Selective silicon-on-insulator isolation structure and methodIBM·Filed 2005·Granted Feb 5, 2008·8 cites·14 claims
- 1381US7411227B2CMOS silicide metal gate integrationIBM·Filed 2006·Granted Aug 12, 2008·7 cites·16 claims
- 1480US7429752B2Method and structure for forming strained SI for CMOS devicesIBM·Filed 2006·Granted Sep 30, 2008·4 cites·14 claims
- 1577US7112481B2Method for forming self-aligned dual salicide in CMOS technologiesIBM·Filed 2005·Granted Sep 26, 2006·5 cites·20 claims
- 1674US7655557B2CMOS silicide metal gate integrationIBM·Filed 2008·Granted Feb 2, 2010·4 cites·9 claims
- 1772US7129126B2Method and structure for forming strained Si for CMOS devicesIBM·Filed 2003·Granted Oct 31, 2006·9 cites·21 claims
- 1870US6927117B2Method for integration of silicide contacts and silicide gate metalsIBM·Filed 2003·Granted Aug 9, 2005·15 cites·26 claims
- 1969US7928443B2Method and structure for forming strained SI for CMOS devicesIBM·Filed 2010·Granted Apr 19, 2011·1 cites·20 claims
- 2069US7923786B2Selective silicon-on-insulator isolation structure and methodIBM·Filed 2007·Granted Apr 12, 2011·3 cites·17 claims
- 2167US7550338B2Method and structure for forming strained SI for CMOS devicesIBM·Filed 2007·Granted Jun 23, 2009·1 cites·4 claims
- 2263US6974736B2Method of forming FET silicide gate structures incorporating inner spacersIBM·Filed 2004·Granted Dec 13, 2005·10 cites·20 claims
- 2359US7700951B2Method and structure for forming strained Si for CMOS devicesIBM·Filed 2008·Granted Apr 20, 2010·0 cites·12 claims
- 2459US6876040B1Dense SRAM cells with selective SOIIBM·Filed 2003·Granted Apr 5, 2005·8 cites·9 claims
- 2554US7064025B1Method for forming self-aligned dual salicide in CMOS technologiesIBM·Filed 2004·Granted Jun 20, 2006·4 cites·21 claims
- 2652US7081397B2Trench sidewall passivation for lateral RIE in a selective silicon-on-insulator process flowIBM·Filed 2004·Granted Jul 25, 2006·5 cites·20 claims
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