Inventor · disambiguated record
Edgardo F. Klass
Also filed as: KLASS EDGARDO · KLASS EDGARDO F
54 granted patents·2 pending applications·689 citations·filing 1996–2020
98Inventor score
Top patents by PatentIndex Score
56 records- 0194US5917355AEdge-triggered staticized dynamic flip-flop with conditional shut-off mechanismSUN MICROSYSTEMS INC·Filed 1997·Granted Jun 29, 1999·110 cites·28 claims
- 0293US8332698B2Scan latch with phase-free scan enableTANG BO·Filed 2010·Granted Dec 11, 2012·12 cites·18 claims
- 0393US7977976B1Self-gating synchronizerAPPLE INC·Filed 2010·Granted Jul 12, 2011·12 cites·25 claims
- 0491US8635503B2Scan latch with phase-free scan enableAPPLE INC·Filed 2012·Granted Jan 21, 2014·8 cites·10 claims
- 0591US5898330AEdge-triggered staticized dynamic flip-flop with scan circuitrySUN MICROSYSTEMS INC·Filed 1997·Granted Apr 27, 1999·80 cites·20 claims
- 0687US7245150B2Combined multiplex or/flopPA SEMI INC·Filed 2005·Granted Jul 17, 2007·17 cites·7 claims
- 0787US6023179AMethod of implementing a scan flip-flop using an edge-triggered staticized dynamic flip-flopSUN MICROSYSTEMS INC·Filed 1997·Granted Feb 8, 2000·55 cites·21 claims
- 0886US9973191B2Power saving with dual-rail supply voltage schemeAPPLE INC·Filed 2016·Granted May 15, 2018·5 cites·20 claims
- 0983US6536022B1Two pole coupling noise analysis model for submicron integrated circuit design verificationSUN MICROSYSTEMS INC·Filed 2000·Granted Mar 18, 2003·39 cites·14 claims
- 1082US7411409B2Digital leakage detector that detects transistor leakage current in an integrated circuitPA SEMI INC·Filed 2005·Granted Aug 12, 2008·12 cites·21 claims
- 1181US8341578B2Clock gater with test features and low setup timeCAMPBELL BRIAN J·Filed 2010·Granted Dec 25, 2012·5 cites·20 claims
- 1280US5933038AFlip-flop with logic function incorporated therein with minimal time penaltySUN MICROSYSTEMS INC·Filed 1997·Granted Aug 3, 1999·39 cites·27 claims
- 1380US5825224AEdge-triggered dual-rail dynamic flip-flop with self-shut-off mechanismSUN MICROSYSTEMS INC·Filed 1996·Granted Oct 20, 1998·40 cites·20 claims
- 1478US8712752B2IR(voltage) drop analysis in integrated circuit timingLAU BETTY Y·Filed 2011·Granted Apr 29, 2014·9 cites·20 claims
- 1578US7843244B1Low latency synchronizer circuitAPPLE INC·Filed 2009·Granted Nov 30, 2010·7 cites·20 claims
- 1678US6121807ASingle phase edge-triggered dual-rail dynamic flip-flopSUN MICROSYSTEMS INC·Filed 1999·Granted Sep 19, 2000·30 cites·12 claims
- 1774US8650527B2Method and software tool for analyzing and reducing the failure rate of an integrated circuitAPPLE INC·Filed 2012·Granted Feb 11, 2014·3 cites·20 claims
- 1874US7779372B2Clock gater with test features and low setup timeAPPLE INC·Filed 2007·Granted Aug 17, 2010·6 cites·15 claims
- 1974US6043696AMethod for implementing a single phase edge-triggered dual-rail dynamic flip-flopFiled 1997·Granted Mar 28, 2000·29 cites·15 claims
- 2069US7454674B2Digital jitter detectorPA SEMI INC·Filed 2006·Granted Nov 18, 2008·5 cites·18 claims
- 2168US7461305B1System and method for detecting and preventing race condition in circuitsSUN MICROSYSTEMS INC·Filed 2005·Granted Dec 2, 2008·5 cites·15 claims
- 2268US7373569B2Pulsed flop with scan circuitryPA SEMI INC·Filed 2005·Granted May 13, 2008·5 cites·18 claims
- 2366US8327310B1Method and software tool for analyzing and reducing the failure rate of an integrated circuitOLIVA ANTONIETTA·Filed 2011·Granted Dec 4, 2012·2 cites·19 claims
- 2466US5920218ASingle-phase edge-triggered dual-rail dynamic flip-flopSUN MICROSYSTEMS INC·Filed 1996·Granted Jul 6, 1999·19 cites·19 claims
- 2564US8301943B2Pulse flop with enhanced scan implementationKLASS EDGARDO F·Filed 2010·Granted Oct 30, 2012·2 cites·17 claims
- 2664US5889417AApparatus and method for improving the noise immunity of a dynamic logic signal repeaterSUN MICROSYSTEMS INC·Filed 1996·Granted Mar 30, 1999·19 cites·20 claims
- 2762US8134387B2Self-gating synchronizerTANG BO·Filed 2011·Granted Mar 13, 2012·1 cites·20 claims
- 2862US6911854B2Clock skew tolerant clocking schemeSUN MICROSYSTEMS INC·Filed 2003·Granted Jun 28, 2005·9 cites·32 claims
- 2962US6828852B2Active pulsed scheme for driving long interconnectsSUN MICROSYSTEMS INC·Filed 2002·Granted Dec 7, 2004·13 cites·4 claims
- 3062US6222404B1Edge-triggered dual-rail dynamic flip-flop with an enhanced self-shut-off mechanismSUN MICROSYSTEMS INC·Filed 1999·Granted Apr 24, 2001·18 cites·17 claims
- 3158US8305125B2Low latency synchronizer circuitTANG BO·Filed 2010·Granted Nov 6, 2012·1 cites·24 claims
- 3257US11500019B2Area-aware test pattern coverage optimizationAPPLE INC·Filed 2020·Granted Nov 15, 2022·0 cites·16 claims
- 3356US8397199B2Versatile method and tool for simulation of aged transistorsSONI APURVA H·Filed 2010·Granted Mar 12, 2013·2 cites·20 claims
- 3456US8125211B2Apparatus and method for testing driver writeability strength on an integrated circuitJAIN ASHISH R·Filed 2009·Granted Feb 28, 2012·2 cites·20 claims
- 3555US6624664B2Clocked full-rail differential logic with sense amplifiersSUN MICROSYSTEMS INC·Filed 2002·Granted Sep 23, 2003·7 cites·16 claims
- 3655US6614264B2Method for increasing the load capacity of full-rail differential logicSUN MICROSYSTEMS INC·Filed 2002·Granted Sep 2, 2003·7 cites·16 claims
- 3754US7319344B2Pulsed flop with embedded logicPA SEMI INC·Filed 2005·Granted Jan 15, 2008·2 cites·11 claims
- 3854US6018254ANon-blocking delayed clocking system for domino logicSUN MICROSYSTEMS INC·Filed 1997·Granted Jan 25, 2000·13 cites·20 claims
- 3950US11204384B1Methods and systems for switchable logic to recover integrated circuits with short circuitsAPPLE INC·Filed 2018·Granted Dec 21, 2021·0 cites·20 claims
- 4050US8947070B2Apparatus and method for testing driver writeability strength on an integrated circuitJAIN ASHISH R·Filed 2012·Granted Feb 3, 2015·0 cites·20 claims
- 4149US8154275B2Apparatus and method for testing sense amplifier thresholds on an integrated circuitJAIN ASHISH R·Filed 2009·Granted Apr 10, 2012·2 cites·12 claims
- 4247US6703867B1Clocked full-rail differential logic with sense amplifier and shut-offSUN MICROSYSTEMS INC·Filed 2002·Granted Mar 9, 2004·4 cites·22 claims
- 4346US7088144B2Conditional precharge design in staticized dynamic flip-flop with clock enableSUN MICROSYSTEMS INC·Filed 2004·Granted Aug 8, 2006·4 cites·6 claims
- 4446US5880609ANon-blocking multiple phase clocking scheme for dynamic logicSUN MICROSYSTEMS INC·Filed 1997·Granted Mar 9, 1999·9 cites·20 claims
- 4544US9503086B1Lockup latch for subthreshold operationAPPLE INC·Filed 2015·Granted Nov 22, 2016·0 cites·20 claims
- 4643US6741113B1Modified high speed flop design with self adjusting, data selective, evaluation windowSUN MICROSYSTEMS INC·Filed 2003·Granted May 25, 2004·2 cites·20 claims
- 4743US5983013AMethod for generating non-blocking delayed clocking signals for domino logicSUN MICROSYSTEMS INC·Filed 1997·Granted Nov 9, 1999·16 cites·20 claims
- 4841US6353339B1Modified domino logic circuit with high input noise rejectionSUN MICROSYSTEMS INC·Filed 2000·Granted Mar 5, 2002·2 cites·20 claims
- 4941US2011016367A1Skew tolerant scannable master/slave flip-flop including embedded logicTANG BO·Filed 2009·Application pending·0 cites
- 5040US7977998B2Apparatus and method for testing level shifter voltage thresholds on an integrated circuitAPPLE INC·Filed 2009·Granted Jul 12, 2011·0 cites·20 claims
Showing the top 50 of 56 patent records by PatentIndex Score.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →