Inventor · disambiguated record
Jeffrey C. Shearer
Also filed as: SHEARER JEFFREY · SHEARER JEFFREY C
32 granted patents·1 pending application·114 citations·filing 2014–2022
96Inventor score
Top patents by PatentIndex Score
33 records- 0198US9450095B1Single spacer for complementary metal oxide semiconductor process flowIBM·Filed 2016·Granted Sep 20, 2016·24 cites·16 claims
- 0296US10074730B2Forming stacked nanowire semiconductor deviceIBM·Filed 2016·Granted Sep 11, 2018·11 cites·17 claims
- 0395US10229854B1FinFET gate cut after dummy gate removalIBM·Filed 2017·Granted Mar 12, 2019·11 cites·11 claims
- 0495US9842739B2Method and structure for enabling high aspect ratio sacrificial gatesIBM·Filed 2016·Granted Dec 12, 2017·8 cites·16 claims
- 0595US9318574B2Method and structure for enabling high aspect ratio sacrificial gatesIBM·Filed 2014·Granted Apr 19, 2016·16 cites·15 claims
- 0691USRE50613EFinFET gate cut after dummy gate removalADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2022·Granted Sep 30, 2025·1 cites·38 claims
- 0790US9659779B2Method and structure for enabling high aspect ratio sacrificial gatesIBM·Filed 2014·Granted May 23, 2017·7 cites·16 claims
- 0889US9882048B2Gate cut on a vertical field effect transistor with a defined-width inorganic maskIBM·Filed 2016·Granted Jan 30, 2018·5 cites·12 claims
- 0989US9536744B1Enabling large feature alignment marks with sidewall image transfer patterningIBM·Filed 2015·Granted Jan 3, 2017·5 cites·14 claims
- 1088US10249753B2Gate cut on a vertical field effect transistor with a defined-width inorganic maskIBM·Filed 2017·Granted Apr 2, 2019·4 cites·20 claims
- 1187US10249533B1Method and structure for forming a replacement contactIBM·Filed 2018·Granted Apr 2, 2019·6 cites·20 claims
- 1287US9859212B1Multi-level air gap formation in dual-damascene structureIBM·Filed 2016·Granted Jan 2, 2018·4 cites·20 claims
- 1385US10224239B2Multi-level air gap formation in dual-damascene structureIBM·Filed 2017·Granted Mar 5, 2019·3 cites·20 claims
- 1483US11024715B2FinFET gate cut after dummy gate removalTESSERA INC·Filed 2020·Granted Jun 1, 2021·1 cites·20 claims
- 1581US11222820B2Self-aligned gate cap including an etch-stop layerIBM·Filed 2018·Granted Jan 11, 2022·2 cites·9 claims
- 1681US9754942B2Single spacer for complementary metal oxide semiconductor process flowIBM·Filed 2016·Granted Sep 5, 2017·2 cites·18 claims
- 1777US10629698B2Method and structure for enabling high aspect ratio sacrificial gatesIBM·Filed 2017·Granted Apr 21, 2020·1 cites·15 claims
- 1876US10586733B2Multi-level air gap formation in dual-damascene structureIBM·Filed 2019·Granted Mar 10, 2020·1 cites·20 claims
- 1972US9748146B1Single spacer for complementary metal oxide semiconductor process flowIBM·Filed 2016·Granted Aug 29, 2017·1 cites·20 claims
- 2070US10796957B2Buried contact to provide reduced VFET feature-to-feature tolerance requirementsIBM·Filed 2017·Granted Oct 6, 2020·1 cites·7 claims
- 2163US10600868B2FinFET gate cut after dummy gate removalTESSERA INC·Filed 2019·Granted Mar 24, 2020·0 cites·19 claims
- 2262US10396181B2Forming stacked nanowire semiconductor deviceIBM·Filed 2018·Granted Aug 27, 2019·0 cites·20 claims
- 2360US12464809B2Vertical field effect transistor with minimal contact to gate erosionIBM·Filed 2021·Granted Nov 4, 2025·0 cites·20 claims
- 2459US11257716B2Self-aligned gate cap including an etch-stop layerIBM·Filed 2019·Granted Feb 22, 2022·0 cites·9 claims
- 2557US10256326B2Forming stacked nanowire semiconductor deviceIBM·Filed 2016·Granted Apr 9, 2019·0 cites·13 claims
- 2657US10204827B2Multi-level air gap formation in dual-damascene structureIBM·Filed 2017·Granted Feb 12, 2019·0 cites·20 claims
- 2756US10446452B2Method and structure for enabling controlled spacer RIEIBM·Filed 2017·Granted Oct 15, 2019·0 cites·14 claims
- 2855US9716184B2Enabling large feature alignment marks with sidewall image transfer patterningIBM·Filed 2016·Granted Jul 25, 2017·0 cites·20 claims
- 2953US11605717B2Wrapped-around contact for vertical field effect transistor top source-drainIBM·Filed 2020·Granted Mar 14, 2023·0 cites·7 claims
- 3052US10804148B2Buried contact to provide reduced VFET feature-to-feature tolerance requirementsIBM·Filed 2017·Granted Oct 13, 2020·0 cites·6 claims
- 3151US9627277B2Method and structure for enabling controlled spacer RIEIBM·Filed 2015·Granted Apr 18, 2017·0 cites·10 claims
- 3250US2022406776A1Stacked fet with different channel materialsIBM·Filed 2021·Application pending·0 cites
- 3345US10304692B1Method of forming field effect transistor (FET) circuits, and forming integrated circuit (IC) chips with the FET circuitsIBM·Filed 2017·Granted May 28, 2019·0 cites·20 claims
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