Inventor · disambiguated record
Karen Darbinyan
Also filed as: DARBINYAN KAREN
11 granted patents·223 citations·filing 2002–2023
90Inventor score
Top patents by PatentIndex Score
11 records- 0193US7415640B1Methods and apparatuses that reduce the size of a repair data container for repairable memoriesVIRAGE LOGIC CORP·Filed 2003·Granted Aug 19, 2008·86 cites·35 claims
- 0286US7290186B1Method and apparatus for a command based bist for testing memoriesVIRAGE LOGIC CORP·Filed 2003·Granted Oct 30, 2007·45 cites·25 claims
- 0386US7149924B1Apparatus, method, and system having a pin to activate the self-test and repair instructionsVIRAGE LOGIC CORP·Filed 2002·Granted Dec 12, 2006·42 cites·19 claims
- 0485US7673264B1System and method for verifying IP integrity in system-on-chip (SOC) designVIRAGE LOGIC CORP·Filed 2007·Granted Mar 2, 2010·22 cites·22 claims
- 0583US9541591B2Periodic signal measurement using statistical samplingSYNOPSYS INC·Filed 2015·Granted Jan 10, 2017·3 cites·19 claims
- 0680US9336342B2Memory hard macro partition optimization for testing embedded memoriesZORIAN YERVANT·Filed 2011·Granted May 10, 2016·9 cites·9 claims
- 0776US7898882B2Architecture, system and method for compressing repair data in an integrated circuit (IC) designSYNOPSYS INC·Filed 2007·Granted Mar 1, 2011·9 cites·15 claims
- 0875US11527298B1On-chip memory diagnosticsSYNOPSYS INC·Filed 2021·Granted Dec 13, 2022·1 cites·20 claims
- 0967US8295108B2Architecture, system and method for compressing repair data in an integrated circuit (IC) designDARBINYAN KAREN·Filed 2011·Granted Oct 23, 2012·4 cites·17 claims
- 1060US9514258B2Generation of memory structural model based on memory layoutAMIRKHANYAN KAREN·Filed 2012·Granted Dec 6, 2016·2 cites·21 claims
- 1156US12469527B2In situ delay measurements on integrated circuits using live data and pulse width modulationSYNOPSYS INC·Filed 2023·Granted Nov 11, 2025·0 cites·18 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →