Inventor · disambiguated record
Jose J. Estabil
Also filed as: ESTABIL JOSE J
10 granted patents·536 citations·filing 2004–2010
93Inventor score
Technology areasH10P
Top patents by PatentIndex Score
10 records- 0198US8344745B2Test structures for evaluating a fabrication of a die or a waferTAU METRIX INC·Filed 2006·Granted Jan 1, 2013·90 cites·16 claims
- 0298US7736916B2System and apparatus for using test structures inside of a chip during the fabrication of the chipTAU METRIX INC·Filed 2007·Granted Jun 15, 2010·97 cites·11 claims
- 0397US7256055B2System and apparatus for using test structures inside of a chip during the fabrication of the chipTAU METRIX INC·Filed 2004·Granted Aug 14, 2007·134 cites·31 claims
- 0495US8990759B2Contactless technique for evaluating a fabrication of a waferAGHABABAZADEH MAJID·Filed 2010·Granted Mar 24, 2015·59 cites·22 claims
- 0595US7423288B2Technique for evaluating a fabrication of a die and waferTAU METRIX INC·Filed 2007·Granted Sep 9, 2008·26 cites·40 claims
- 0694US7605597B2Intra-chip power and test signal generation for use with test structures on wafersTAU METRIX INC·Filed 2007·Granted Oct 20, 2009·18 cites·10 claims
- 0794US7220990B2Technique for evaluating a fabrication of a die and waferTAU METRIX INC·Filed 2004·Granted May 22, 2007·59 cites·59 claims
- 0888US7730434B2Contactless technique for evaluating a fabrication of a waferTAU METRIX INC·Filed 2004·Granted Jun 1, 2010·24 cites·57 claims
- 0988US7339388B2Intra-clip power and test signal generation for use with test structures on wafersTAU METRIX INC·Filed 2004·Granted Mar 4, 2008·25 cites·26 claims
- 1082US7723724B2System for using test structures to evaluate a fabrication of a waferTAU METRIX INC·Filed 2008·Granted May 25, 2010·4 cites·10 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →