Inventor · disambiguated record
Pawan Kulshreshtha
Also filed as: KULSHRESHTHA PAWAN
8 granted patents·1 pending application·95 citations·filing 2001–2023
86Inventor score
Technology areasG06F
Top patents by PatentIndex Score
9 records- 0194US8745561B1System and method for common path pessimism reduction in timing analysis to guide remedial transformations of a circuit designCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Jun 3, 2014·36 cites·20 claims
- 0293US10467365B1Systems and methods for calculating common clock path pessimism for hierarchical timing analysis in an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Nov 5, 2019·21 cites·14 claims
- 0388US10169501B1Timing context generation with multi-instance blocks for hierarchical analysisCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jan 1, 2019·7 cites·20 claims
- 0488US10037394B1Hierarchical timing analysis for multi-instance blocksCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jul 31, 2018·8 cites·20 claims
- 0584US10460059B1System and method for generating reduced standard delay format files for gate level simulationCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 29, 2019·8 cites·17 claims
- 0679US10133842B1Methods, systems, and articles of manufacture for multi-mode, multi-corner physical optimization of electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Nov 20, 2018·4 cites·22 claims
- 0768US11188696B1Method, system, and product for deferred merge based method for graph based analysis pessimism reductionCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Nov 30, 2021·1 cites·20 claims
- 0863US7647220B2Transistor-level timing analysis using embedded simulationCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted Jan 12, 2010·10 cites·36 claims
- 0952US2025124204A1Efficient method for the latch timing analysis of electronic designsXILINX INC·Filed 2023·Application pending·0 cites
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