Inventor · disambiguated record
Pooja M. Kotecha
Also filed as: KOTECHA POOJA M
8 granted patents·1 pending application·87 citations·filing 2004–2019
86Inventor score
Files withIBM9
Top patents by PatentIndex Score
9 records- 0192US7581201B2System and method for sign-off timing closure of a VLSI chipIBM·Filed 2007·Granted Aug 25, 2009·35 cites·19 claims
- 0284US7996812B2Method of minimizing early-mode violations causing minimum impact to a chip designIBM·Filed 2008·Granted Aug 9, 2011·16 cites·18 claims
- 0383US7895556B2Method for optimizing an unrouted design to reduce the probability of timing problems due to coupling and long wire routesIBM·Filed 2007·Granted Feb 22, 2011·13 cites·18 claims
- 0480US10417663B2Ephemeral geofence campaign systemIBM·Filed 2016·Granted Sep 17, 2019·2 cites·19 claims
- 0579US7987440B2Method and system for efficient validation of clock skews during hierarchical static timing analysisIBM·Filed 2009·Granted Jul 26, 2011·10 cites·11 claims
- 0674US10168857B2Virtual reality for cognitive messagingIBM·Filed 2016·Granted Jan 1, 2019·3 cites·20 claims
- 0764US10949884B2Ephemeral geofence campaign systemIBM·Filed 2019·Granted Mar 16, 2021·0 cites·20 claims
- 0861US6958545B2Method for reducing wiring congestion in a VLSI chip designIBM·Filed 2004·Granted Oct 25, 2005·8 cites·11 claims
- 0943US2007234259A1Cell placement in circuit designIBM·Filed 2006·Application pending·0 cites
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