Inventor · disambiguated record
Mark E. Schuelein
Also filed as: SCHUELEIN MARK · SCHUELEIN MARK E · SCHUELEIN MARK EDWARD
13 granted patents·103 citations·filing 1996–2013
91Inventor score
Top patents by PatentIndex Score
13 records- 0187US8760208B2Latch with a feedback circuitDIKE CHARLES E·Filed 2012·Granted Jun 24, 2014·12 cites·19 claims
- 0276US7659762B2Clock synchronizerINTEL CORP·Filed 2007·Granted Feb 9, 2010·10 cites·12 claims
- 0370US6956421B1Slave-less edge-triggered flip-flopINTEL CORP·Filed 2003·Granted Oct 18, 2005·15 cites·14 claims
- 0465US7236032B2Ultra-drowsy circuitINTEL CORP·Filed 2006·Granted Jun 26, 2007·4 cites·5 claims
- 0563US7095255B2Ultra-drowsy circuitINTEL CORP·Filed 2004·Granted Aug 22, 2006·9 cites·17 claims
- 0663US5870326AInformation encoding by multiple line selectionINTEL CORP·Filed 1997·Granted Feb 9, 1999·23 cites·8 claims
- 0751US7649385B2Logic with state retentive sleep modeINTEL CORP·Filed 2006·Granted Jan 19, 2010·2 cites·8 claims
- 0849US6113648AMethod and apparatus for protecting gate electrodes of target transistors in the gate array from gate charging by employing free transistors in the gate arrayINTEL CORP·Filed 1998·Granted Sep 5, 2000·11 cites·6 claims
- 0948US9276575B2Low leakage state retention synchronizerJAYAPAL SENTHILKUMAR·Filed 2013·Granted Mar 1, 2016·1 cites·13 claims
- 1047US5793069AApparatus for protecting gate electrodes of target transistors in a gate array from gate charging by employing free transistors in the gate arrayINTEL CORP·Filed 1996·Granted Aug 11, 1998·10 cites·14 claims
- 1145US6995435B2Apparatus and circuit having reduced leakage current and method thereforINTEL CORP·Filed 2004·Granted Feb 7, 2006·2 cites·16 claims
- 1245US6800908B2Apparatus and circuit having reduced leakage current and method thereforINTEL CORP·Filed 2002·Granted Oct 5, 2004·2 cites·21 claims
- 1340US7139951B2Scan enabled storage deviceINTEL CORP·Filed 2004·Granted Nov 21, 2006·2 cites·18 claims
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