Inventor · disambiguated record
Joel A. Silberman
Also filed as: SILBERMAN JOEL · SILBERMAN JOEL A · SILBERMAN JOEL ABRAHAM
94 granted patents·2 pending applications·847 citations·filing 1996–2020
99Inventor score
Top patents by PatentIndex Score
96 records- 0197US8576000B23D chip stack skew reduction with resonant clock and inductive couplingKIM JAE-JOON·Filed 2011·Granted Nov 5, 2013·24 cites·5 claims
- 0292US9941189B2Counter-flow expanding channels for enhanced two-phase heat removalIBM·Filed 2015·Granted Apr 10, 2018·7 cites·24 claims
- 0392US7689812B2Method and system for restoring register mapper states for an out-of-order microprocessorIBM·Filed 2007·Granted Mar 30, 2010·29 cites·18 claims
- 0490US10714420B1High cutoff frequency metal-insulator-metal capacitors implemented using via contact configurationsIBM·Filed 2019·Granted Jul 14, 2020·7 cites·20 claims
- 0590US8587357B2AC supply noise reduction in a 3D stack with voltage sensing and clock shiftingKIM JAE-JOON·Filed 2011·Granted Nov 19, 2013·13 cites·25 claims
- 0690US6014763AAt-speed scan testingIBM·Filed 1998·Granted Jan 11, 2000·75 cites·27 claims
- 0789US8380964B2Processor including age tracking of issue queue instructionsIBM·Filed 2009·Granted Feb 19, 2013·18 cites·14 claims
- 0888US10564976B2Scalable dependency matrix with multiple summary bits in an out-of-order processorIBM·Filed 2017·Granted Feb 18, 2020·5 cites·20 claims
- 0988US8466739B23D chip stack skew reduction with resonant clock and inductive couplingKIM JAE-JOON·Filed 2012·Granted Jun 18, 2013·11 cites·20 claims
- 1087US10727159B2Counter-flow expanding channels for enhanced two-phase heat removalIBM·Filed 2019·Granted Jul 28, 2020·3 cites·20 claims
- 1184US6356990B1Set-associative cache memory having a built-in set prediction arrayIBM·Filed 2000·Granted Mar 12, 2002·45 cites·10 claims
- 1282US8476771B2Configuration of connections in a 3D stack of integrated circuitsSCHEUERMANN MICHAEL R·Filed 2011·Granted Jul 2, 2013·9 cites·25 claims
- 1381US9713286B2Active control for two-phase coolingIBM·Filed 2015·Granted Jul 18, 2017·2 cites·7 claims
- 1479US8489863B2Processor including age tracking of issue queue instructionsBISHOP JAMES WILSON·Filed 2012·Granted Jul 16, 2013·5 cites·7 claims
- 1578US11464137B2Active control for two-phase coolingIBM·Filed 2018·Granted Oct 4, 2022·1 cites·8 claims
- 1677US11256509B2Instruction fusion after register renameIBM·Filed 2017·Granted Feb 22, 2022·2 cites·5 claims
- 1777US9986662B2Active control for two-phase coolingIBM·Filed 2017·Granted May 29, 2018·1 cites·5 claims
- 1876US6914453B2Integrated logic and latch design with clock gating at static input signalsIBM·Filed 2003·Granted Jul 5, 2005·18 cites·23 claims
- 1975US8127116B2Dependency matrix with reduced area and power consumptionISLAM SAIFUL·Filed 2009·Granted Feb 28, 2012·10 cites·18 claims
- 2075US6229358B1Delayed matching signal generator and frequency multiplier using scaled delay networksIBM·Filed 1999·Granted May 8, 2001·28 cites·22 claims
- 2174US6604191B1Method and apparatus for accelerating instruction fetching for a processorIBM·Filed 2000·Granted Aug 5, 2003·21 cites·25 claims
- 2272US10231359B2Active control for two-phase coolingIBM·Filed 2015·Granted Mar 12, 2019·1 cites·5 claims
- 2371US10572264B2Completing coalesced global completion table entries in an out-of-order processorIBM·Filed 2017·Granted Feb 25, 2020·1 cites·20 claims
- 2470US6825695B1Unified local clock buffer structuresIBM·Filed 2003·Granted Nov 30, 2004·14 cites·24 claims
- 2569US8928350B2Programming the behavior of individual chips or strata in a 3D stack of integrated circuitsPANG LIANG-TECK·Filed 2012·Granted Jan 6, 2015·2 cites·23 claims
- 2669US6961276B2Random access memory having an adaptable latencyIBM·Filed 2003·Granted Nov 1, 2005·18 cites·22 claims
- 2769US6744282B1Latching dynamic logic structure, and integrated circuit including sameIBM·Filed 2003·Granted Jun 1, 2004·13 cites·20 claims
- 2868US8519735B2Programming the behavior of individual chips or strata in a 3D stack of integrated circuitsPANG LIANG-TECK·Filed 2011·Granted Aug 27, 2013·2 cites·2 claims
- 2968US6138208AMultiple level cache memory with overlapped L1 and L2 memory accessIBM·Filed 1998·Granted Oct 24, 2000·52 cites·11 claims
- 3066US6600959B1Method and apparatus for implementing microprocessor control logic using dynamic programmable logic arraysIBM·Filed 2000·Granted Jul 29, 2003·12 cites·20 claims
- 3165US7165006B2Scan chain disable function for power savingIBM·Filed 2004·Granted Jan 16, 2007·8 cites·9 claims
- 3264US10727158B2Counter-flow expanding channels for enhanced two-phase heat removalIBM·Filed 2019·Granted Jul 28, 2020·0 cites·20 claims
- 3364US9087909B2Hybrid extremely thin silicon-on-insulator (ETSOI) structure to minimize noise coupling from TSVIBM·Filed 2013·Granted Jul 21, 2015·1 cites·8 claims
- 3463US11204772B2Coalescing global completion table entries in an out-of-order processorIBM·Filed 2020·Granted Dec 21, 2021·0 cites·20 claims
- 3561US6927615B2Low skew, power efficient local clock signal generation systemIBM·Filed 2003·Granted Aug 9, 2005·7 cites·20 claims
- 3661US6816396B2Apparatus for detecting multiple hits in a CAMRAM memory arrayIBM·Filed 2003·Granted Nov 9, 2004·11 cites·14 claims
- 3759US10529648B2Counter-flow expanding channels for enhanced two-phase heat removalIBM·Filed 2018·Granted Jan 7, 2020·0 cites·20 claims
- 3859US6944088B2Apparatus and method for generating memory access signals, and memory accessed using said signalsIBM·Filed 2002·Granted Sep 13, 2005·6 cites·21 claims
- 3959US6941335B2Random carry-in for floating-point operationsIBM·Filed 2001·Granted Sep 6, 2005·6 cites·17 claims
- 4059US6076140ASet associative cache memory system with reduced power consumptionIBM·Filed 1998·Granted Jun 13, 2000·22 cites·5 claims
- 4158US7225422B2Wire trimmed programmable logic arrayIBM·Filed 2003·Granted May 29, 2007·6 cites·11 claims
- 4258US6229338B1Method and apparatus for reducing dynamic programmable logic array propagation delayIBM·Filed 2000·Granted May 8, 2001·8 cites·18 claims
- 4357US10564979B2Coalescing global completion table entries in an out-of-order processorIBM·Filed 2017·Granted Feb 18, 2020·0 cites·20 claims
- 4456US11281745B2Half-precision floating-point arrays at low overheadIBM·Filed 2019·Granted Mar 22, 2022·0 cites·20 claims
- 4555US10083880B2Hybrid ETSOI structure to minimize noise coupling from TSVIBM·Filed 2017·Granted Sep 25, 2018·0 cites·18 claims
- 4655US7170328B2Scannable latchIBM·Filed 2004·Granted Jan 30, 2007·5 cites·8 claims
- 4753US9653615B2Hybrid ETSOI structure to minimize noise coupling from TSVIBM·Filed 2013·Granted May 16, 2017·0 cites·11 claims
- 4853US7746140B2Scannable latchIBM·Filed 2006·Granted Jun 29, 2010·1 cites·7 claims
- 4953US6021461AMethod for reducing power consumption in a set associative cache memory systemIBM·Filed 1999·Granted Feb 1, 2000·20 cites·6 claims
- 5052US11106469B2Instruction selection mechanism with class-dependent age-arrayIBM·Filed 2019·Granted Aug 31, 2021·0 cites·20 claims
Showing the top 50 of 96 patent records by PatentIndex Score.
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