Inventor · disambiguated record
Kalipatnam Vivek Rao
Also filed as: RAO KALIPATNAM · RAO KALIPATNAM V · RAO KALIPATNAM VIVEK
24 granted patents·10 pending applications·1,455 citations·filing 1985–2018
97Inventor score
Files withTEXAS INSTRUMENTS INC12MEARS TECHNOLOGIES INC9RJ MEARS LLC8ATOMERA INC3RJ MEARS LLC STATE OF INC DELA1
Top patents by PatentIndex Score
34 records- 0198US10741436B2Method for making a semiconductor device including non-monocrystalline stringer adjacent a superlattice-sti interfaceATOMERA INC·Filed 2018·Granted Aug 11, 2020·30 cites·23 claims
- 0298US10636879B2Method for making DRAM with recessed channel array transistor (RCAT) including a superlatticeATOMERA INC·Filed 2018·Granted Apr 28, 2020·30 cites·25 claims
- 0398US10367064B2Semiconductor device with recessed channel array transistor (RCAT) including a superlatticeATOMERA INC·Filed 2018·Granted Jul 30, 2019·44 cites·20 claims
- 0498US7928425B2Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methodsMEARS TECHNOLOGIES INC·Filed 2008·Granted Apr 19, 2011·113 cites·27 claims
- 0598US7812339B2Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structuresMEARS TECHNOLOGIES INC·Filed 2008·Granted Oct 12, 2010·109 cites·23 claims
- 0698US7781827B2Semiconductor device with a vertical MOSFET including a superlattice and related methodsMEARS TECHNOLOGIES INC·Filed 2008·Granted Aug 24, 2010·136 cites·26 claims
- 0798US7659539B2Semiconductor device including a floating gate memory cell with a superlattice channelMEARS TECHNOLOGIES INC·Filed 2006·Granted Feb 9, 2010·118 cites·17 claims
- 0898US7586116B2Semiconductor device having a semiconductor-on-insulator configuration and a superlatticeMEARS TECHNOLOGIES INC·Filed 2006·Granted Sep 8, 2009·111 cites·23 claims
- 0998US7514328B2Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetweenMEARS TECHNOLOGIES INC·Filed 2006·Granted Apr 7, 2009·123 cites·20 claims
- 1098US7491587B2Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layerMEARS TECHNOLOGIES INC·Filed 2006·Granted Feb 17, 2009·110 cites·21 claims
- 1198US7446002B2Method for making a semiconductor device comprising a superlattice dielectric interface layerMEARS TECHNOLOGIES INC·Filed 2005·Granted Nov 4, 2008·120 cites·21 claims
- 1298US7202494B2FINFET including a superlatticeRJ MEARS LLC·Filed 2006·Granted Apr 10, 2007·140 cites·23 claims
- 1390US4874716AProcess for fabricating integrated circuit structure with extremely smooth polysilicone dielectric interfaceTEXAS INSTRUMENTS INC·Filed 1988·Granted Oct 17, 1989·64 cites·17 claims
- 1470US5298451ARecessed and sidewall-sealed poly-buffered LOCOS isolation methodsTEXAS INSTRUMENTS INC·Filed 1991·Granted Mar 29, 1994·45 cites·8 claims
- 1562US5294563ASidewall-sealed and sandwiched poly-buffered locos isolation methodsTEXAS INSTRUMENTS INC·Filed 1992·Granted Mar 15, 1994·31 cites·7 claims
- 1658US5369051ASidewall-sealed poly-buffered LOCOS isolationTEXAS INSTRUMENTS INC·Filed 1992·Granted Nov 29, 1994·33 cites·3 claims
- 1755US5159428ASidewall-sealed poly-buffered LOCOS isolationTEXAS INSTRUMENTS INC·Filed 1990·Granted Oct 27, 1992·28 cites·3 claims
- 1850US4806201AUse of sidewall oxide to reduce filamentsTEXAS INSTRUMENTS INC·Filed 1988·Granted Feb 21, 1989·18 cites·14 claims
- 1946US4799992AInterlevel dielectric fabrication processTEXAS INSTRUMENTS INC·Filed 1985·Granted Jan 24, 1989·13 cites·14 claims
- 2045US6239003B1Method of simultaneous fabrication of isolation and gate regions in a semiconductor deviceTEXAS INSTRUMENTS INC·Filed 1999·Granted May 29, 2001·12 cites·14 claims
- 2144US2015214339A1Techniques for ion implantation of narrow semiconductor structuresVARIAN SEMICONDUCTOR EQUIPMENT·Filed 2014·Application pending·0 cites
- 2243US2006289049A1Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor LayerRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 2341US2007063185A1Semiconductor device including a front side strained superlattice layer and a back side stress layerRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 2441US2007063186A1Method for making a semiconductor device including a front side strained superlattice layer and a back side stress layerRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 2540US5114530AInterlevel dielectric processTEXAS INSTRUMENTS INC·Filed 1990·Granted May 19, 1992·10 cites·8 claims
- 2640US2006292765A1Method for Making a FINFET Including a SuperlatticeRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 2740US2006263980A1Method for making a semiconductor device including a floating gate memory cell with a superlattice channelRJ MEARS LLC STATE OF INC DELA·Filed 2006·Application pending·0 cites
- 2840US2006243964A1Method for making a semiconductor device having a semiconductor-on-insulator configuration and a superlatticeRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 2940US2006267130A1Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice TherebetweenRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 3039US6297130B1Recessed, sidewall-sealed and sandwiched poly-buffered LOCOS isolation methodsTEXAS INSTRUMENTS INC·Filed 1993·Granted Oct 2, 2001·8 cites·10 claims
- 3139US2011215299A1Semiconductor device including a superlattice and dopant diffusion retarding implants and related methodsMEARS TECHNOLOGIES INC·Filed 2011·Application pending·0 cites
- 3238US2006011905A1Semiconductor device comprising a superlattice dielectric interface layerRJ MEARS LLC·Filed 2005·Application pending·0 cites
- 3334US5608256ARecessed sidewall-sealed and sandwiched poly-buffered LOCOS isolation regions, VLSI structures and methodsTEXAS INSTRUMENTS INC·Filed 1995·Granted Mar 4, 1997·3 cites·20 claims
- 3433US4878996AMethod for reduction of filaments between electrodesTEXAS INSTRUMENTS INC·Filed 1989·Granted Nov 7, 1989·6 cites·11 claims
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