Inventor

CHU ALBERT M

US84 patents

⚠️ This page may combine multiple inventors who share the name “CHU ALBERT M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHU ALBERT M

IBM

Ultra dense vertical transport FET circuits

IC layout optimization to improve yield

Transistor delay circuits

High density vertical field effect transistor multiplexer

Vertical transistors with merged active area regions

3D vertical FET with top and bottom gate contacts

Metal fill optimization for self-aligned double patterning

Glitch free delay line multiplexing technique

Method for combining refresh operation with parity validation in a DRAM-based content addressable memory (CAM)

Use of search lines as global bitlines in a cam design

Digital delay line with low insertion delay

Ultra dense vertical transport FET circuits

Methods and circuits for generating physically unclonable function

Voltage detection circuit and circuit for generating a trigger flag signal

Apparatus and method for improved triggering and oscillation suppression of ESD clamping devices

High density static random-access memory

Stacked FET SRAM

Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same

3D vertical FET with top and bottom gate contacts

3D vertical FET with top and bottom gate contacts

3D vertical FET with top and bottom gate contacts

Process variation skew in an SRAM column architecture

Contact structure for power delivery on semiconductor device

Vertical-transport field-effect transistor with backside source/drain connections

VTFET circuit with optimized output

Stacked field effect transistor contacts

Reduced capacitance between power via bar and gates

Stacked field effect transistor

Subtractive source drain contact for stacked devices

Source/drain contact at tight cell boundary

Interconnect structures with vias having vertical and horizontal sections

Wrap around metal via structure

Vertical transport field effect transistor (VTFET) with backside wraparound contact

Vertical transistor with reduced cell height

Method and structure of forming independent contact for staggered CFET

Pass-through wiring in notched interconnect

Vertical-transport field-effect transistor with backside gate contact

High density stacked vertical transistor static random access memory structure

Stacked layer memory suitable for SRAM and having a long cell

Local interconnect for cross coupling

CHU ALBERT M

Embedded photon emission calibration (EPEC)

Alternate power gating enablement

Reduced current leakage in RC ESD clamps

Current leakage in RC ESD clamps

INFINEON TECHNOLOGIES CORP

Frequency range trimming for a delay line

Delay element using a delay locked loop

Delay-locked-loop (DLL) having symmetrical rising and falling clock edge type delays

SIEMENS AG

Clock latency compensation circuit for DDR timing

BRACERAS GEORGE M

Read only memory (ROM) with redundancy

INT BUSNIESS MACHINES CORPORATION

Reliable gate contacts over active areas