Inventor · disambiguated record
John R. Riley
Also filed as: RILEY III JOHN REGINALD · RILEY JOHN · RILEY JOHN R · RILEY JOHN REGINALD
10 granted patents·4 pending applications·56 citations·filing 1993–2023
87Inventor score
Top patents by PatentIndex Score
14 records- 0193US9378788B2Negative bitline write assist circuit and method for operating the sameKOLAR PRAMOD·Filed 2012·Granted Jun 28, 2016·19 cites·23 claims
- 0281US9575891B2Sidecar SRAM for high granularity in floor plan aspect ratioADVANCED MICRO DEVICES INC·Filed 2014·Granted Feb 21, 2017·6 cites·17 claims
- 0381US9508414B2Memory cell supply voltage reduction prior to write cycleADVANCED MICRO DEVICES INC·Filed 2013·Granted Nov 29, 2016·8 cites·17 claims
- 0480US9818460B2Negative bitline write assist circuit and method for operating the sameINTEL CORP·Filed 2016·Granted Nov 14, 2017·4 cites·23 claims
- 0577US9355743B2Memory array test logicADVANCED MICRO DEVICES INC·Filed 2014·Granted May 31, 2016·6 cites·13 claims
- 0649US10902893B2Negative bitline write assist circuit and method for operating the sameINTEL CORP·Filed 2017·Granted Jan 26, 2021·0 cites·21 claims
- 0749US10818326B2Negative bitline write assist circuit and method for operating the sameINTEL CORP·Filed 2017·Granted Oct 27, 2020·0 cites·22 claims
- 0844US7630228B2Methods and apparatuses for operating memoryINTEL CORP·Filed 2007·Granted Dec 8, 2009·1 cites·19 claims
- 0943US2024118826A1Memory array utilizing bitcells with single-ended read circuitryINTEL CORP·Filed 2022·Application pending·0 cites
- 1042US5456146ABar stock prealignment collarMKM MACHINE TOOL CO INC·Filed 1993·Granted Oct 10, 1995·12 cites·49 claims
- 1142US2024221825A1Register file arrays with multiplexed read path circuitryRILEY JOHN R·Filed 2023·Application pending·0 cites
- 1239US2024005982A1Multi-ported memory array utilizing bitcells with balanced p-n diffusion layoutsGHOSH AMLAN·Filed 2022·Application pending·0 cites
- 1330US2016379706A1Dual voltage asymmetric memory cellINTEL CORP·Filed 2013·Application pending·0 cites
- 1428US8068371B2Methods and systems to improve write response times of memory cellsMERCHANT FEROZE A·Filed 2008·Granted Nov 29, 2011·0 cites·20 claims
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