Inventor · disambiguated record
William R. Bryg
Also filed as: BRYG WILLIAM · BRYG WILLIAM R
39 granted patents·2,265 citations·filing 1985–2008
99Inventor score
Files withHEWLETT PACKARD CO26INST THE DEV OF EMERGING ARCHI7HEWLETT PACKARD DEVELOPMENT CO3INTEL CORP2SIVARAMAKRISHNAN RAMASWAMY1
Top patents by PatentIndex Score
39 records- 0194US6430670B1Apparatus and method for a virtual hashed page tableHEWLETT PACKARD CO·Filed 2000·Granted Aug 6, 2002·86 cites·26 claims
- 0294US4809160APrivilege level checking instruction for implementing a secure hierarchical computer systemHEWLETT PACKARD CO·Filed 1985·Granted Feb 28, 1989·188 cites·3 claims
- 0394US4713755ACache memory consistency control with explicit software instructionsHEWLETT PACKARD CO·Filed 1985·Granted Dec 15, 1987·174 cites·5 claims
- 0488US5586297APartial cache line write transactions in a computing system with a write back cacheHEWLETT PACKARD CO·Filed 1994·Granted Dec 17, 1996·139 cites·12 claims
- 0588US5530933AMultiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the busHEWLETT PACKARD CO·Filed 1994·Granted Jun 25, 1996·139 cites·4 claims
- 0687US6088780APage table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual addressINST THE DEV OF EMERGING ARCHI·Filed 1997·Granted Jul 11, 2000·141 cites·35 claims
- 0786US4928239ACache memory with variable fetch and replacement schemesHEWLETT PACKARD CO·Filed 1989·Granted May 22, 1990·100 cites·8 claims
- 0883US6393544B1Method and apparatus for calculating a page table index from a virtual addressINST THE DEV OF EMERGING ARCHI·Filed 1999·Granted May 21, 2002·113 cites·20 claims
- 0983US5724538AComputer memory address control apparatus utilizing hashed address tags in page tables which are compared to a combined address tag and index which are longer than the basic data width of the associated computerHEWLETT PACKARD CO·Filed 1996·Granted Mar 3, 1998·108 cites·11 claims
- 1082US4777589ADirect input/output in a virtual memory systemHEWLETT PACKARD CO·Filed 1985·Granted Oct 11, 1988·83 cites·7 claims
- 1181US5603004AMethod for decreasing time penalty resulting from a cache miss in a multi-level cache systemHEWLETT PACKARD CO·Filed 1994·Granted Feb 11, 1997·102 cites·29 claims
- 1279US5940872ASoftware and hardware-managed translation lookaside bufferINTEL CORP·Filed 1996·Granted Aug 17, 1999·89 cites·20 claims
- 1377US6199144B1Method and apparatus for transferring data in a computer systemINTEL CORP·Filed 1997·Granted Mar 6, 2001·77 cites·20 claims
- 1477US5535352AAccess hints for input/output address translation mechanismsHEWLETT PACKARD CO·Filed 1994·Granted Jul 9, 1996·79 cites·9 claims
- 1575US6304932B1Queue-based predictive flow control mechanism with indirect determination of queue fullnessHEWLETT PACKARD CO·Filed 2000·Granted Oct 16, 2001·19 cites·3 claims
- 1674US6128706AApparatus and method for a load bias--load with intent to semaphoreINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Oct 3, 2000·68 cites·15 claims
- 1774US6049851AMethod and apparatus for checking cache coherency in a computer architectureHEWLETT PACKARD CO·Filed 1994·Granted Apr 11, 2000·65 cites·10 claims
- 1870US4739471AMethod and means for moving bytes in a reduced instruction set computerHEWLETT PACKARD CO·Filed 1985·Granted Apr 19, 1988·41 cites·11 claims
- 1969US6408373B2Method and apparatus for pre-validating regions in a virtual addressing schemeINST THE DEV OF EMERGING ARCHI·Filed 2001·Granted Jun 18, 2002·12 cites·7 claims
- 2066US5995967AForming linked lists using content addressable memoryHEWLETT PACKARD CO·Filed 1996·Granted Nov 30, 1999·41 cites·13 claims
- 2165US6874070B2System and method for memory interleaving using cell map with entry grouping for higher-way interleavingHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Mar 29, 2005·11 cites·17 claims
- 2265US5293607AFlexible N-way memory interleavingHEWLETT PACKARD CO·Filed 1991·Granted Mar 8, 1994·44 cites·9 claims
- 2365US5060137AExplicit instructions for control of translation lookaside buffersHEWLETT PACKARD CO·Filed 1988·Granted Oct 22, 1991·37 cites·7 claims
- 2463US6820086B1Forming linked lists using content addressable memoryHEWLETT PACKARD DEVELOPMENT CO·Filed 1999·Granted Nov 16, 2004·23 cites·15 claims
- 2563US6216214B1Apparatus and method for a virtual hashed page tableINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Apr 10, 2001·34 cites·17 claims
- 2662US6006325AMethod and apparatus for instruction and data serialization in a computer processorINST THE DEV OF EMERGING ARCHI·Filed 1996·Granted Dec 21, 1999·39 cites·17 claims
- 2760US8464009B2Method for memory interleave support with a ceiling maskSIVARAMAKRISHNAN RAMASWAMY·Filed 2008·Granted Jun 11, 2013·2 cites·14 claims
- 2856US4914582ACache tag lookasideHEWLETT PACKARD CO·Filed 1986·Granted Apr 3, 1990·23 cites·7 claims
- 2955US7103728B2System and method for memory migration in distributed-memory multi-processor systemsHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Sep 5, 2006·4 cites·19 claims
- 3053US6182176B1Queue-based predictive flow control mechanismHEWLETT PACKARD CO·Filed 1994·Granted Jan 30, 2001·22 cites·1 claims
- 3152US5515522ACoherence index generation for use by an input/output adapter located outside of the processor to detect whether the updated version of data resides within the cacheHEWLETT PACKARD CO·Filed 1994·Granted May 7, 1996·25 cites·21 claims
- 3251US5528766AMultiple arbitration schemeHEWLETT PACKARD CO·Filed 1994·Granted Jun 18, 1996·22 cites·3 claims
- 3348US6079012AComputer that selectively forces ordered execution of store and load operations between a CPU and a shared memoryHEWLETT PACKARD CO·Filed 1997·Granted Jun 20, 2000·22 cites·8 claims
- 3447US5519838AFast pipelined distributed arbitration schemeHEWLETT PACKARD CO·Filed 1994·Granted May 21, 1996·19 cites·6 claims
- 3545US5784708ATranslation mechanism for input/output addressesHEWLETT PACKARD CO·Filed 1996·Granted Jul 21, 1998·19 cites·11 claims
- 3642US6230248B1Method and apparatus for pre-validating regions in a virtual addressing schemeINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted May 8, 2001·14 cites·1 claims
- 3741US6108721AMethod and apparatus for ensuring data consistency between an i/o channel and a processorHEWLETT PACKARD CO·Filed 1998·Granted Aug 22, 2000·12 cites·23 claims
- 3841US5586274AAtomic operation control schemeHEWLETT PACKARD CO·Filed 1994·Granted Dec 17, 1996·15 cites·6 claims
- 3940US5278985ASoftware method for implementing dismissible instructions on a computerHEWLETT PACKARD CO·Filed 1990·Granted Jan 11, 1994·14 cites·3 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →