Inventor · disambiguated record
Haitham Akkary
Also filed as: AKKARY HAITHAM · AKKARY HAITHAM H
73 granted patents·9 pending applications·2,917 citations·filing 1993–2023
99Inventor score
Top patents by PatentIndex Score
82 records- 0199US11455641B1System and method to identify user and device behavior abnormalities to continuously measure transaction riskACCEPTTO CORP·Filed 2021·Granted Sep 27, 2022·53 cites·18 claims
- 0299US11005839B1System and method to identify abnormalities to continuously measure transaction riskACCEPTTO CORP·Filed 2019·Granted May 11, 2021·155 cites·14 claims
- 0398US10387980B1Method and system for consumer based access control for identity informationSHAHIDZADEH NAHAL·Filed 2016·Granted Aug 20, 2019·66 cites·18 claims
- 0498US10325259B1Dynamic authorization with adaptive levels of assuranceACCEPTTO CORP·Filed 2015·Granted Jun 18, 2019·44 cites·30 claims
- 0597US11367323B1System and method for secure pair and unpair processing using a dynamic level of assurance (LOA) scoreACCEPTTO CORP·Filed 2021·Granted Jun 21, 2022·21 cites·6 claims
- 0697US11101993B1Authentication and authorization through derived behavioral credentials using secured paired communication devicesACCEPTTO CORP·Filed 2021·Granted Aug 24, 2021·25 cites·11 claims
- 0797US10951606B1Continuous authentication through orchestration and risk calculation post-authorization system and methodACCEPTTO CORP·Filed 2020·Granted Mar 16, 2021·72 cites·8 claims
- 0896US12086808B1System and method for using user context and behavior for providing access to a secure computer networkSECUREAUTH CORP·Filed 2022·Granted Sep 10, 2024·4 cites·15 claims
- 0996US11552940B1System and method for continuous authentication of user entity identity using context and behavior for real-time modeling and anomaly detectionACCEPTTO CORP·Filed 2021·Granted Jan 10, 2023·6 cites·11 claims
- 1096US11133929B1System and method of biobehavioral derived credentials identificationACCEPTTO CORP·Filed 2019·Granted Sep 28, 2021·23 cites·23 claims
- 1196US10572874B1Dynamic authorization with adaptive levels of assuranceSHAHIDZADEH NAHAL·Filed 2017·Granted Feb 25, 2020·21 cites·28 claims
- 1296US9426183B2Authentication policy orchestration for a user deviceACCEPTTO CORP·Filed 2014·Granted Aug 23, 2016·29 cites·42 claims
- 1395US10715555B1Hierarchical multi-transaction policy orchestrated authentication and authorizationACCEPTTO CORP·Filed 2018·Granted Jul 14, 2020·11 cites·7 claims
- 1495US10148699B1Authentication policy orchestration for a user deviceACCEPTTO CORP·Filed 2017·Granted Dec 4, 2018·13 cites·19 claims
- 1595US8180977B2Transactional memory in out-of-order processorsRAJWAR RAVI·Filed 2006·Granted May 15, 2012·48 cites·31 claims
- 1694US11250530B1Method and system for consumer based access control for identity informationACCEPTTO CORP·Filed 2019·Granted Feb 15, 2022·7 cites·8 claims
- 1794US9742809B1Authentication policy orchestration for a user deviceACCEPTTO CORP·Filed 2016·Granted Aug 22, 2017·11 cites·24 claims
- 1893US11562455B1Method and system for identity verification and authorization of request by checking against an active user directory of identity service entities selected by an identity information ownerSECUREAUTH CORP·Filed 2022·Granted Jan 24, 2023·2 cites·12 claims
- 1992US6493820B2Processor having multiple program counters and trace buffers outside an execution pipelineINTEL CORP·Filed 2000·Granted Dec 10, 2002·66 cites·19 claims
- 2091US11657396B1System and method for bluetooth proximity enforced authenticationSECUREAUTH CORP·Filed 2022·Granted May 23, 2023·1 cites·20 claims
- 2191US10691597B1Method and system for processing big dataMIFRONTIERS CORP·Filed 2020·Granted Jun 23, 2020·18 cites·22 claims
- 2289US6182210B1Processor having multiple program counters and trace buffers outside an execution pipelineINTEL CORP·Filed 1997·Granted Jan 30, 2001·118 cites·29 claims
- 2389US5956753AMethod and apparatus for handling speculative memory access operationsINTEL CORP·Filed 1997·Granted Sep 21, 1999·142 cites·31 claims
- 2489US5526510AMethod and apparatus for implementing a single clock cycle line replacement in a data cache unitINTEL CORP·Filed 1994·Granted Jun 11, 1996·157 cites·12 claims
- 2588US5881262AMethod and apparatus for blocking execution of and storing load operations during their executionINTEL CORP·Filed 1997·Granted Mar 9, 1999·126 cites·45 claims
- 2688US5751983AOut-of-order processor with a memory subsystem which handles speculatively dispatched load operationsFiled 1995·Granted May 12, 1998·140 cites·26 claims
- 2787US12056975B1System and method for secure pair and unpair processing using a dynamic level of assurance (LOA) scoreSECUREAUTH CORP·Filed 2022·Granted Aug 6, 2024·1 cites·6 claims
- 2887US11321712B1System and method for on-demand level of assurance depending on a predetermined authentication systemACCEPTTO CORP·Filed 2020·Granted May 3, 2022·2 cites·9 claims
- 2987US7809903B2Coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactionsINTEL CORP·Filed 2005·Granted Oct 5, 2010·17 cites·19 claims
- 3086US8190859B2Critical section detection and prediction mechanism for hardware lock elisionAKKARY HAITHAM·Filed 2006·Granted May 29, 2012·15 cites·16 claims
- 3186US6247121B1Multithreading processor with thread predictorINTEL CORP·Filed 1998·Granted Jun 12, 2001·94 cites·22 claims
- 3284US11888839B1Continuous authentication through orchestration and risk calculation post-authentication system and methodSECUREAUTH CORP·Filed 2023·Granted Jan 30, 2024·1 cites·9 claims
- 3384US6772324B2Processor having multiple program counters and trace buffers outside an execution pipelineINTEL CORP·Filed 2002·Granted Aug 3, 2004·36 cites·32 claims
- 3483US8180967B2Transactional memory virtualizationRAJWAR RAVI·Filed 2006·Granted May 15, 2012·12 cites·33 claims
- 3582US5613083ATranslation lookaside buffer that is non-blocking in response to a miss for use within a microprocessor capable of processing speculative instructionsINTEL CORP·Filed 1994·Granted Mar 18, 1997·93 cites·30 claims
- 3681US5671444AMethods and apparatus for caching data in a non-blocking manner using a plurality of fill buffersINTEL CORPORAITON·Filed 1996·Granted Sep 23, 1997·104 cites·39 claims
- 3781US5420991AApparatus and method for maintaining processing consistency in a computer system having multiple processorsINTEL CORP·Filed 1994·Granted May 30, 1995·89 cites·20 claims
- 3880US11349879B1System and method for multi-transaction policy orchestration with first and second level derived policies for authentication and authorizationACCEPTTO CORP·Filed 2020·Granted May 31, 2022·1 cites·21 claims
- 3980US5724536AMethod and apparatus for blocking execution of and storing load operations during their executionINTEL CORP·Filed 1994·Granted Mar 3, 1998·74 cites·32 claims
- 4079US5606670AMethod and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer systemINTEL CORP·Filed 1996·Granted Feb 25, 1997·80 cites·32 claims
- 4177US5577200AMethod and apparatus for loading and storing misaligned data on an out-of-order execution computer systemINTEL CORP·Filed 1995·Granted Nov 19, 1996·80 cites·52 claims
- 4275US8627030B2Late lock acquire mechanism for hardware lock elision (HLE)AKKARY HAITHAM·Filed 2007·Granted Jan 7, 2014·7 cites·24 claims
- 4374US6697912B2Prioritized content addressable memoryINTEL CORP·Filed 2003·Granted Feb 24, 2004·15 cites·9 claims
- 4472US11392739B1Method and system for processing big dataMLFRONTIERS CORP·Filed 2019·Granted Jul 19, 2022·2 cites·24 claims
- 4571US5636374AMethod and apparatus for performing operations based upon the addresses of microinstructionsINTEL CORP·Filed 1995·Granted Jun 3, 1997·68 cites·48 claims
- 4670US7418552B2Memory disambiguation for large instruction windowsINTEL CORP·Filed 2003·Granted Aug 26, 2008·13 cites·30 claims
- 4770US6463522B1Memory system for ordering load and store instructions in a processor that performs multithread executionINTEL CORP·Filed 1997·Granted Oct 8, 2002·50 cites·37 claims
- 4870US6240509B1Out-of-pipeline trace buffer for holding instructions that may be re-executed following misspeculationINTEL CORP·Filed 1997·Granted May 29, 2001·55 cites·26 claims
- 4970US5680565AMethod and apparatus for performing page table walks in a microprocessor capable of processing speculative instructionsINTEL CORP·Filed 1993·Granted Oct 21, 1997·53 cites·27 claims
- 5070US5680572ACache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffersINTEL CORP·Filed 1996·Granted Oct 21, 1997·58 cites·28 claims
Showing the top 50 of 82 patent records by PatentIndex Score.
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