Inventor · disambiguated record
Alexander Miretsky
Also filed as: MIRETSKY ALEXANDER
9 granted patents·1 pending application·77 citations·filing 2000–2015
86Inventor score
Technology areasG06F
Top patents by PatentIndex Score
10 records- 0189US10007619B2Multi-threaded translation and transaction re-ordering for memory management unitsQUALCOMM INC·Filed 2015·Granted Jun 26, 2018·11 cites·38 claims
- 0282US9824015B2Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable mediaQUALCOMM INC·Filed 2015·Granted Nov 21, 2017·4 cites·33 claims
- 0376US6553487B1Device and method for performing high-speed low overhead context switchMOTOROLA INC·Filed 2000·Granted Apr 22, 2003·26 cites·18 claims
- 0474US7409572B1Low power memory controller with leaded double data rate DRAM package arranged on a two layer printed circuit boardLSI CORP·Filed 2003·Granted Aug 5, 2008·19 cites·6 claims
- 0571US7657774B1Low power memory controller with leaded double data rate DRAM package on a two layer printed circuit boardLSI LOGIC CORP·Filed 2008·Granted Feb 2, 2010·5 cites·18 claims
- 0661US6647462B1Apparatus and a method for providing decoded informationMOTOROLA INC·Filed 2000·Granted Nov 11, 2003·10 cites·21 claims
- 0759US10019380B2Providing memory management functionality using aggregated memory management units (MMUs)QUALCOMM INC·Filed 2015·Granted Jul 10, 2018·1 cites·44 claims
- 0859US7849256B2Memory controller with ring bus for interconnecting memory clients to memory devicesADVANCED MICRO DEVICES INC·Filed 2006·Granted Dec 7, 2010·1 cites·21 claims
- 0946US2011093644A1Memory Controller With Ring Bus for Interconnecting Memory Clients to Memory DevicesKRUGER WARREN F·Filed 2010·Application pending·0 cites
- 1042US9836410B2Burst translation look-aside bufferQUALCOMM INC·Filed 2015·Granted Dec 5, 2017·0 cites·25 claims
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