Inventor · disambiguated record
Thomas Philip Speier
Also filed as: SPEIER THOMAS · SPEIER THOMAS P · SPEIER THOMAS PHILIP
65 granted patents·17 pending applications·193 citations·filing 2002–2024
98Inventor score
Files withQUALCOMM INC34MICROSOFT TECHNOLOGY LICENSING LLC21IBM16DIEFFENDERFER JAMES NORRIS3ADVANCED RISC MACH LTD2
Top patents by PatentIndex Score
82 records- 0185US7500045B2Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing systemQUALCOMM INC·Filed 2005·Granted Mar 3, 2009·15 cites·21 claims
- 0284US7523265B2Systems and arrangements for promoting a line to exclusive in a fill buffer of a cacheIBM·Filed 2005·Granted Apr 21, 2009·14 cites·20 claims
- 0380US10896135B1Facilitating page table entry (PTE) maintenance in processor-based devicesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Jan 19, 2021·3 cites·20 claims
- 0479US8386716B2Apparatus and methods to reduce castouts in a multi-level cache hierarchyQUALCOMM INC·Filed 2011·Granted Feb 26, 2013·4 cites·29 claims
- 0578US11550723B2Method, apparatus, and system for memory bandwidth aware data prefetchingQUALCOMM INC·Filed 2018·Granted Jan 10, 2023·2 cites·26 claims
- 0678US8078803B2Apparatus and methods to reduce castouts in a multi-level cache hierarchySPEIER THOMAS PHILIP·Filed 2008·Granted Dec 13, 2011·8 cites·29 claims
- 0777US11232042B2Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based systemMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Jan 25, 2022·2 cites·28 claims
- 0877US7353319B2Method and apparatus for segregating shared and non-shared data in cache memory banksQUALCOMM INC·Filed 2005·Granted Apr 1, 2008·8 cites·22 claims
- 0976US11704253B2Performing speculative address translation in processor-based devicesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted Jul 18, 2023·1 cites·19 claims
- 1076US9329930B2Cache memory error detection circuits for detecting bit flips in valid indicators in cache memory following invalidate operations, and related methods and processor-based systemsQUALCOMM INC·Filed 2014·Granted May 3, 2016·4 cites·28 claims
- 1176US9026744B2Enforcing strongly-ordered requests in a weakly-ordered processingHOFMANN RICHARD GERARD·Filed 2005·Granted May 5, 2015·8 cites·17 claims
- 1272US12093186B2Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based systemMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2023·Granted Sep 17, 2024·0 cites·8 claims
- 1372US11061820B2Optimizing access to page table entries in processor-based devicesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Jul 13, 2021·1 cites·20 claims
- 1471US8782356B2Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regionsPANAVICH JASON LAWRENCE·Filed 2011·Granted Jul 15, 2014·4 cites·34 claims
- 1570US12164441B2Method, apparatus, and system for storing memory encryption realm key IDsQUALCOMM INC·Filed 2023·Granted Dec 10, 2024·0 cites·9 claims
- 1670US10956162B2Operand-based reach explicit dataflow processors, and related methods and computer-readable mediaMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Mar 23, 2021·1 cites·30 claims
- 1770US9110830B2Determining cache hit/miss of aliased addresses in virtually-tagged cache(s), and related systems and methodsDIEFFENDERFER JAMES NORRIS·Filed 2012·Granted Aug 18, 2015·3 cites·29 claims
- 1870US8352682B2Methods and apparatus for issuing memory barrier commands in a weakly ordered storage systemQUALCOMM INC·Filed 2009·Granted Jan 8, 2013·4 cites·22 claims
- 1969US6961276B2Random access memory having an adaptable latencyIBM·Filed 2003·Granted Nov 1, 2005·18 cites·22 claims
- 2068US6970962B2Transfer request pipeline throttlingIBM·Filed 2003·Granted Nov 29, 2005·13 cites·19 claims
- 2167US7127562B2Ensuring orderly forward progress in granting snoop castout requestsIBM·Filed 2003·Granted Oct 24, 2006·12 cites·12 claims
- 2266US7752396B2Promoting a line from shared to exclusive in a cacheIBM·Filed 2008·Granted Jul 6, 2010·3 cites·6 claims
- 2366US6948053B2Efficiently calculating a branch target addressIBM·Filed 2002·Granted Sep 20, 2005·11 cites·41 claims
- 2465US11842196B2Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructionsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted Dec 12, 2023·0 cites·23 claims
- 2565US11803482B2Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based systemMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Oct 31, 2023·0 cites·16 claims
- 2665US6907502B2Method for moving snoop pushes to the front of a request queueIBM·Filed 2002·Granted Jun 14, 2005·10 cites·27 claims
- 2763US12093164B1Efficiently replacing software breakpoint instructions in processor-based devicesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2023·Granted Sep 17, 2024·0 cites·20 claims
- 2863US7421529B2Method and apparatus to clear semaphore reservation for exclusive access to shared memoryQUALCOMM INC·Filed 2005·Granted Sep 2, 2008·2 cites·16 claims
- 2963US6816962B2Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructionsIBM·Filed 2002·Granted Nov 9, 2004·9 cites·16 claims
- 3062US11188334B2Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructionsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Nov 30, 2021·0 cites·17 claims
- 3162US6976132B2Reducing latency of a snoop tenureIBM·Filed 2003·Granted Dec 13, 2005·8 cites·20 claims
- 3261US11789874B2Method, apparatus, and system for storing memory encryption realm key IDsQUALCOMM INC·Filed 2019·Granted Oct 17, 2023·0 cites·10 claims
- 3360US7319578B2Digital power monitor and adaptive self-tuning power managementIBM·Filed 2005·Granted Jan 15, 2008·2 cites·15 claims
- 3458US8499208B2Method and apparatus for scheduling BIST routinesDIEFFENDERFER JAMES NORRIS·Filed 2006·Granted Jul 30, 2013·3 cites·30 claims
- 3558US7395372B2Method and system for providing cache set selection which is power optimizedIBM·Filed 2003·Granted Jul 1, 2008·6 cites·16 claims
- 3657US11687453B2Cache-based trace logging using tags in an upper-level cacheMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Jun 27, 2023·0 cites·20 claims
- 3757US7089376B2Reducing snoop response time for snoopers without copies of requested data via snoop filteringIBM·Filed 2003·Granted Aug 8, 2006·8 cites·13 claims
- 3857US2025298616A1Compare commandADVANCED RISC MACH LTD·Filed 2024·Application pending·0 cites
- 3956US12373350B2Cache-line retention hint information for conditional write instructionADVANCED RISC MACH LTD·Filed 2023·Granted Jul 29, 2025·0 cites·19 claims
- 4056US11126437B2Load instruction with final read indicator field to invalidate a buffer or cache entry storing the memory address holding load dataMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Sep 21, 2021·0 cites·18 claims
- 4155US11226910B2Ticket based request flow controlQUALCOMM INC·Filed 2020·Granted Jan 18, 2022·0 cites·44 claims
- 4254US6985972B2Dynamic cache coherency snooper presence with variable snoop latencyIBM·Filed 2002·Granted Jan 10, 2006·3 cites·20 claims
- 4353US11366769B1Enabling peripheral device messaging via application portals in processor-based devicesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted Jun 21, 2022·0 cites·20 claims
- 4453US7685373B2Selective snooping by snoop masters to locate updated dataIBM·Filed 2008·Granted Mar 23, 2010·0 cites·9 claims
- 4552US11119770B2Performing atomic store-and-invalidate operations in processor-based devicesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Sep 14, 2021·0 cites·20 claims
- 4651US11868269B2Tracking memory block access frequency in processor-based devicesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted Jan 9, 2024·0 cites·18 claims
- 4751US11061822B2Method, apparatus, and system for reducing pipeline stalls due to address translation missesQUALCOMM INC·Filed 2018·Granted Jul 13, 2021·0 cites·24 claims
- 4851US9292442B2Methods and apparatus for improving performance of semaphore management sequences across a coherent busQUALCOMM INC·Filed 2013·Granted Mar 22, 2016·0 cites·20 claims
- 4951US7610463B2Method and apparatus for performing an atomic semaphore operationQUALCOMM INC·Filed 2004·Granted Oct 27, 2009·1 cites·29 claims
- 5050US11561896B2Cache-based trace logging using tags in an upper-level cacheMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted Jan 24, 2023·0 cites·20 claims
Showing the top 50 of 82 patent records by PatentIndex Score.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →