Inventor · disambiguated record
James Norris Dieffenderfer
Also filed as: DIEFFENDERFER JAMES N · DIEFFENDERFER JAMES NORRIS
118 granted patents·30 pending applications·1,330 citations·filing 1989–2021
99Inventor score
Files withQUALCOMM INC64IBM42DIEFFENDERFER JAMES NORRIS10MICROSOFT TECHNOLOGY LICENSING LLC4SMITH RODNEY W3
Top patents by PatentIndex Score
148 records- 0192US5224213APing-pong data buffer for transferring data from one data bus to another data busIBM·Filed 1989·Granted Jun 29, 1993·133 cites·1 claims
- 0290US8438372B2Link stack repair of erroneous speculative updateDIEFFENDERFER JAMES NORRIS·Filed 2011·Granted May 7, 2013·15 cites·27 claims
- 0390US7624256B2System and method wherein conditional instructions unconditionally provide outputQUALCOMM INC·Filed 2005·Granted Nov 24, 2009·24 cites·15 claims
- 0489US7917702B2Data prefetch throttleQUALCOMM INC·Filed 2007·Granted Mar 29, 2011·19 cites·26 claims
- 0589US7152155B2System and method of correcting a branch mispredictionQUALCOMM INC·Filed 2005·Granted Dec 19, 2006·19 cites·17 claims
- 0688US5996092ASystem and method for tracing program execution within a processor before and after a triggering eventIBM·Filed 1996·Granted Nov 30, 1999·127 cites·4 claims
- 0787US7624254B2Segmented pipeline flushing for mispredicted branchesQUALCOMM INC·Filed 2007·Granted Nov 24, 2009·18 cites·1 claims
- 0887US7278012B2Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructionsQUALCOMM INC·Filed 2005·Granted Oct 2, 2007·18 cites·22 claims
- 0986US7587580B2Power efficient instruction prefetch mechanismQUALCOMM INC·Filed 2005·Granted Sep 8, 2009·14 cites·11 claims
- 1085US8904155B2Representing loop branches in a branch history register with multiple bitsDIEFFENDERFER JAMES NORRIS·Filed 2006·Granted Dec 2, 2014·15 cites·33 claims
- 1185US7500045B2Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing systemQUALCOMM INC·Filed 2005·Granted Mar 3, 2009·15 cites·21 claims
- 1285US7366869B2Method and system for optimizing translation lookaside buffer entriesQUALCOMM INC·Filed 2005·Granted Apr 29, 2008·15 cites·14 claims
- 1384US7523265B2Systems and arrangements for promoting a line to exclusive in a fill buffer of a cacheIBM·Filed 2005·Granted Apr 21, 2009·14 cites·20 claims
- 1483US7971044B2Link stack repair of erroneous speculative updateQUALCOMM INC·Filed 2007·Granted Jun 28, 2011·11 cites·23 claims
- 1583US6826747B1System and method for tracing program instructions before and after a trace triggering event within a processorIBM·Filed 1999·Granted Nov 30, 2004·88 cites·19 claims
- 1683US6826656B2Reducing power in a snooping cache based multiprocessor environmentIBM·Filed 2002·Granted Nov 30, 2004·35 cites·27 claims
- 1782US9477478B2Multi level indirect predictor using confidence counter and program counter address filter schemeKOTHARI KULIN N·Filed 2012·Granted Oct 25, 2016·10 cites·17 claims
- 1879US8386716B2Apparatus and methods to reduce castouts in a multi-level cache hierarchyQUALCOMM INC·Filed 2011·Granted Feb 26, 2013·4 cites·29 claims
- 1979US7805588B2Caching memory attribute indicators with cached memory data fieldQUALCOMM INC·Filed 2005·Granted Sep 28, 2010·9 cites·26 claims
- 2079US7426626B2TLB lock indicatorQUALCOMM INC·Filed 2005·Granted Sep 16, 2008·9 cites·18 claims
- 2179US7421568B2Power saving methods and apparatus to selectively enable cache bits based on known processor stateQUALCOMM INC·Filed 2005·Granted Sep 2, 2008·9 cites·18 claims
- 2279US5910930ADynamic control of power management circuitryIBM·Filed 1997·Granted Jun 8, 1999·92 cites·7 claims
- 2378US8078803B2Apparatus and methods to reduce castouts in a multi-level cache hierarchySPEIER THOMAS PHILIP·Filed 2008·Granted Dec 13, 2011·8 cites·29 claims
- 2477US7353319B2Method and apparatus for segregating shared and non-shared data in cache memory banksQUALCOMM INC·Filed 2005·Granted Apr 1, 2008·8 cites·22 claims
- 2576US9026744B2Enforcing strongly-ordered requests in a weakly-ordered processingHOFMANN RICHARD GERARD·Filed 2005·Granted May 5, 2015·8 cites·17 claims
- 2675US7437537B2Methods and apparatus for predicting unaligned memory accessQUALCOMM INC·Filed 2005·Granted Oct 14, 2008·7 cites·18 claims
- 2774US7478228B2Apparatus for generating return address predictions for implicit and explicit subroutine callsQUALCOMM INC·Filed 2006·Granted Jan 13, 2009·5 cites·13 claims
- 2874US7415638B2Pre-decode error handling via branch correctionQUALCOMM INC·Filed 2004·Granted Aug 19, 2008·17 cites·22 claims
- 2973US7984279B2System and method for using a working global history registerQUALCOMM INC·Filed 2006·Granted Jul 19, 2011·6 cites·18 claims
- 3073US7827392B2Sliding-window, block-based branch target address cacheQUALCOMM INC·Filed 2006·Granted Nov 2, 2010·6 cites·16 claims
- 3173US7093058B2Single request data transfer regardless of size and alignmentIBM·Filed 2005·Granted Aug 15, 2006·6 cites·4 claims
- 3273US6834378B2System on a chip bus with automatic pipeline stage insertion for timing closureIBM·Filed 2002·Granted Dec 21, 2004·15 cites·11 claims
- 3372US8943300B2Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode informationSTEMPEL BRIAN MICHAEL·Filed 2008·Granted Jan 27, 2015·5 cites·17 claims
- 3472US7730282B2Method and apparatus for avoiding data dependency hazards in a microprocessor pipeline architecture using a multi-bit age vectorIBM·Filed 2004·Granted Jun 1, 2010·20 cites·13 claims
- 3572US7210024B2Conditional instruction execution via emissary instruction for condition evaluationQUALCOMM INC·Filed 2005·Granted Apr 24, 2007·5 cites·19 claims
- 3671US8782356B2Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regionsPANAVICH JASON LAWRENCE·Filed 2011·Granted Jul 15, 2014·4 cites·34 claims
- 3771US8341383B2Method and a system for accelerating procedure return sequencesDIEFFENDERFER JAMES NORRIS·Filed 2007·Granted Dec 25, 2012·5 cites·32 claims
- 3871US7669039B2Use of register renaming system for forwarding intermediate results between constituent instructions of an expanded instructionQUALCOMM INC·Filed 2007·Granted Feb 23, 2010·5 cites·19 claims
- 3971US5884051ASystem, methods and computer program products for flexibly controlling bus access based on fixed and dynamic prioritiesIBM·Filed 1997·Granted Mar 16, 1999·61 cites·21 claims
- 4071US5809293ASystem and method for program execution tracing within an integrated processorIBM·Filed 1994·Granted Sep 15, 1998·58 cites·29 claims
- 4170US9477476B2Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable mediaQUALCOMM INC·Filed 2012·Granted Oct 25, 2016·3 cites·25 claims
- 4270US9110830B2Determining cache hit/miss of aliased addresses in virtually-tagged cache(s), and related systems and methodsDIEFFENDERFER JAMES NORRIS·Filed 2012·Granted Aug 18, 2015·3 cites·29 claims
- 4370US8352682B2Methods and apparatus for issuing memory barrier commands in a weakly ordered storage systemQUALCOMM INC·Filed 2009·Granted Jan 8, 2013·4 cites·22 claims
- 4470US7934025B2Content terminated DMAQUALCOMM INC·Filed 2007·Granted Apr 26, 2011·5 cites·33 claims
- 4570US7203826B2Method and apparatus for managing a return stackQUALCOMM INC·Filed 2005·Granted Apr 10, 2007·4 cites·25 claims
- 4670US7035958B2Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the targetIBM·Filed 2002·Granted Apr 25, 2006·15 cites·21 claims
- 4769US7698536B2Method and system for providing an energy efficient register fileQUALCOMM INC·Filed 2005·Granted Apr 13, 2010·4 cites·21 claims
- 4869US6961276B2Random access memory having an adaptable latencyIBM·Filed 2003·Granted Nov 1, 2005·18 cites·22 claims
- 4968US7330941B2Global modified indicator to reduce power consumption on cache missQUALCOMM INC·Filed 2005·Granted Feb 12, 2008·4 cites·10 claims
- 5068US7281120B2Apparatus and method for decreasing the latency between an instruction cache and a pipeline processorIBM·Filed 2004·Granted Oct 9, 2007·11 cites·3 claims
Showing the top 50 of 148 patent records by PatentIndex Score.
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