Inventor · disambiguated record
Elyar E. Gasanov
Also filed as: GASANOV ELYAR · GASANOV ELYAR E · GASANOV ELYAR ELDAROVICH
65 granted patents·5 pending applications·1,014 citations·filing 1998–2021
99Inventor score
Files withLSI LOGIC CORP25LSI CORP15FUTUREWEI TECHNOLOGIES INC5PANTELEEV PAVEL A5HUAWEI TECH CO LTD4
Top patents by PatentIndex Score
70 records- 0194US10735138B2Multi-label offset lifting methodFUTUREWEI TECHNOLOGIES INC·Filed 2018·Granted Aug 4, 2020·12 cites·20 claims
- 0293US6324674B2Method and apparatus for parallel simultaneous global and detail routingLSI LOGIC CORP·Filed 1998·Granted Nov 27, 2001·206 cites·36 claims
- 0390US6550045B1Changing clock delays in an integrated circuit for skew optimizationLSI LOGIC CORP·Filed 2001·Granted Apr 15, 2003·88 cites·16 claims
- 0489US6550044B1Method in integrating clock tree synthesis and timing optimization for an integrated circuit designLSI LOGIC CORP·Filed 2001·Granted Apr 15, 2003·59 cites·9 claims
- 0589US6253363B1Net routing using basis element decompositionLSI LOGIC CORP·Filed 1998·Granted Jun 26, 2001·153 cites·24 claims
- 0689US6175950B1Method and apparatus for hierarchical global routing descendLSI LOGIC CORP·Filed 1998·Granted Jan 16, 2001·157 cites·19 claims
- 0785US6564361B1Method and apparatus for timing driven resynthesisLSI LOGIC CORP·Filed 2000·Granted May 13, 2003·44 cites·4 claims
- 0884US9337866B2Apparatus for processing signals carrying modulation-encoded parity bitsLSI CORP·Filed 2013·Granted May 10, 2016·9 cites·20 claims
- 0981US11171742B2Multi-label offset lifting methodFUTUREWEI TECHNOLOGIES INC·Filed 2020·Granted Nov 9, 2021·1 cites·20 claims
- 1081US8850437B2Two-pass linear complexity task schedulerSHUTKIN YURII S·Filed 2011·Granted Sep 30, 2014·8 cites·18 claims
- 1181US6543032B1Method and apparatus for local resynthesis of logic trees with multiple cost functionsLSI LOGIC CORP·Filed 2000·Granted Apr 1, 2003·33 cites·17 claims
- 1279US10567002B2Method and apparatus for encoding and decoding LDPC codesHUAWEI TECH CO LTD·Filed 2019·Granted Feb 18, 2020·3 cites·30 claims
- 1379US6637016B1Assignment of cell coordinatesLSI LOGIC CORP·Filed 2001·Granted Oct 21, 2003·27 cites·13 claims
- 1478US10594339B2Method for generating parity check matrix for low density parity check codingHUAWEI TECH CO LTD·Filed 2018·Granted Mar 17, 2020·4 cites·34 claims
- 1577US9331716B2Systems and methods for area efficient data encodingLSI CORP·Filed 2014·Granted May 3, 2016·6 cites·20 claims
- 1675US11265014B2Method and apparatus for encoding and decoding LDPC codesHUAWEI TECH CO LTD·Filed 2020·Granted Mar 1, 2022·1 cites·20 claims
- 1775US6681373B1Method and apparatus for dynamic buffer and inverter tree optimizationLSI LOGIC CORP·Filed 2000·Granted Jan 20, 2004·22 cites·26 claims
- 1874US8397143B2BCH or reed-solomon decoder with syndrome modificationNEZNANOV ILYA V·Filed 2009·Granted Mar 12, 2013·10 cites·20 claims
- 1971US11664928B2Multi-label offset lifting methodFUTUREWEI TECHNOLOGIES INC·Filed 2021·Granted May 30, 2023·0 cites·20 claims
- 2071US6629304B1Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cellsLSI LOGIC CORP·Filed 2001·Granted Sep 30, 2003·16 cites·25 claims
- 2171US6532582B1Method and apparatus for optimal critical netlist area selectionLSI LOGIC CORP·Filed 2000·Granted Mar 11, 2003·17 cites·27 claims
- 2270US6845495B2Multidirectional routerLSI LOGIC CORP·Filed 2001·Granted Jan 18, 2005·15 cites·30 claims
- 2367US7401313B2Method and apparatus for controlling congestion during integrated circuit design resynthesisLSI CORP·Filed 2005·Granted Jul 15, 2008·4 cites·17 claims
- 2467US6810515B2Process of restructuring logics in ICs for setup and hold time optimizationLSI LOGIC CORP·Filed 2002·Granted Oct 26, 2004·12 cites·18 claims
- 2567US6701493B2Floor plan tester for integrated circuit designLSI LOGIC CORP·Filed 2002·Granted Mar 2, 2004·12 cites·14 claims
- 2667US6637011B1Method and apparatus for quick search for identities applicable to specified formulaLSI LOGIC CORP·Filed 2000·Granted Oct 21, 2003·13 cites·18 claims
- 2766US7496870B2Method of selecting cells in logic restructuringLSI CORP·Filed 2006·Granted Feb 24, 2009·3 cites·16 claims
- 2865US8176397B2Variable redundancy reed-solomon encoderPANTELEEV PAVEL·Filed 2008·Granted May 8, 2012·7 cites·14 claims
- 2965US6615401B1Blocked net buffer insertionLSI LOGIC CORP·Filed 2002·Granted Sep 2, 2003·12 cites·12 claims
- 3064US8656206B2Timer manager architecture based on binary heapGASANOV ELYAR E·Filed 2011·Granted Feb 18, 2014·2 cites·22 claims
- 3164US6470487B1Parallelization of resynthesisLSI LOGIC CORP·Filed 2001·Granted Oct 22, 2002·10 cites·9 claims
- 3263US10862626B2Multi-label offset lifting methodFUTUREWEI TECHNOLOGIES INC·Filed 2019·Granted Dec 8, 2020·0 cites·25 claims
- 3362US10879927B2Compact low density parity check (LDPC) base graphFUTUREWEI TECHNOLOGIES INC·Filed 2018·Granted Dec 29, 2020·1 cites·20 claims
- 3461US8365054B2Soft reed-solomon decoder based on error-and-erasure reed-solomon decoderLSI CORP·Filed 2009·Granted Jan 29, 2013·4 cites·20 claims
- 3559US6868536B2Method to find boolean function symmetriesLSI LOGIC CORP·Filed 2002·Granted Mar 15, 2005·6 cites·15 claims
- 3657US9553612B2Decoding based on randomized hard decisionsSEAGATE TECHNOLOGY LLC·Filed 2015·Granted Jan 24, 2017·1 cites·20 claims
- 3757US8539009B2Parallel true random number generator architectureALISEYCHIK PAVEL A·Filed 2008·Granted Sep 17, 2013·2 cites·21 claims
- 3855US7103865B2Process and apparatus for placement of megacells in ICs designLSI LOGIC CORP·Filed 2003·Granted Sep 5, 2006·4 cites·18 claims
- 3954US7398486B2Method and apparatus for performing logical transformations for global routingLSI CORP·Filed 2004·Granted Jul 8, 2008·4 cites·8 claims
- 4052US7257791B2Multiple buffer insertion in global routingLSI CORP·Filed 2004·Granted Aug 14, 2007·3 cites·20 claims
- 4152US6553551B1Timing recomputationLSI LOGIC CORP·Filed 2001·Granted Apr 22, 2003·2 cites·11 claims
- 4251US8286060B2Scheme for erasure locator polynomial calculation in error-and-erasure decoderPANTELEEV PAVEL A·Filed 2008·Granted Oct 9, 2012·2 cites·18 claims
- 4351US7823050B2Low area architecture in BCH decoderLSICorporation·Filed 2006·Granted Oct 26, 2010·3 cites·1 claims
- 4451US7568175B2Ramptime propagation on designs with cyclesLSI CORP·Filed 2007·Granted Jul 28, 2009·0 cites·5 claims
- 4551US7003739B2Method and apparatus for finding optimal unification substitution for formulas in technology libraryLSI LOGIC CORP·Filed 2003·Granted Feb 21, 2006·2 cites·22 claims
- 4650US8621329B2Reconfigurable BCH decoderPANTELEEV PAVEL A·Filed 2011·Granted Dec 31, 2013·1 cites·20 claims
- 4750US8181096B2Configurable Reed-Solomon decoder based on modified Forney syndromesANDREEV ALEXANDER·Filed 2007·Granted May 15, 2012·2 cites·20 claims
- 4850US6701503B2Overlap remover managerLSI LOGIC CORP·Filed 2002·Granted Mar 2, 2004·1 cites·35 claims
- 4949US8527851B2System and method for using the universal multipole for the implementation of a configurable binary Bose-Chaudhuri-Hocquenghem (BCH) encoder with variable number of errorsANDREEV ALEXANDER E·Filed 2008·Granted Sep 3, 2013·2 cites·12 claims
- 5049US7146591B2Method of selecting cells in logic restructuringLSI LOGIC CORP·Filed 2004·Granted Dec 5, 2006·1 cites·6 claims
Showing the top 50 of 70 patent records by PatentIndex Score.
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