Inventor · disambiguated record
Andrej A. Zolotykh
Also filed as: ZOLOTYKH ANDREJ A
24 granted patents·335 citations·filing 2000–2008
96Inventor score
Top patents by PatentIndex Score
24 records- 0189US6550044B1Method in integrating clock tree synthesis and timing optimization for an integrated circuit designLSI LOGIC CORP·Filed 2001·Granted Apr 15, 2003·59 cites·9 claims
- 0285US6564361B1Method and apparatus for timing driven resynthesisLSI LOGIC CORP·Filed 2000·Granted May 13, 2003·44 cites·4 claims
- 0381US6543032B1Method and apparatus for local resynthesis of logic trees with multiple cost functionsLSI LOGIC CORP·Filed 2000·Granted Apr 1, 2003·33 cites·17 claims
- 0479US6637016B1Assignment of cell coordinatesLSI LOGIC CORP·Filed 2001·Granted Oct 21, 2003·27 cites·13 claims
- 0577US8160242B2Efficient implementation of arithmetical secure hash techniquesGRINCHUK MIKHAIL·Filed 2008·Granted Apr 17, 2012·10 cites·21 claims
- 0677US6487697B1Distribution dependent clustering in buffer insertion of high fanout netsLSI LOGIC CORP·Filed 2001·Granted Nov 26, 2002·24 cites·21 claims
- 0775US6681373B1Method and apparatus for dynamic buffer and inverter tree optimizationLSI LOGIC CORP·Filed 2000·Granted Jan 20, 2004·22 cites·26 claims
- 0871US6651239B1Direct transformation of engineering change orders to synthesized IC chip designsLSI LOGIC CORP·Filed 2001·Granted Nov 18, 2003·16 cites·21 claims
- 0971US6629304B1Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cellsLSI LOGIC CORP·Filed 2001·Granted Sep 30, 2003·16 cites·25 claims
- 1071US6532582B1Method and apparatus for optimal critical netlist area selectionLSI LOGIC CORP·Filed 2000·Granted Mar 11, 2003·17 cites·27 claims
- 1167US6810515B2Process of restructuring logics in ICs for setup and hold time optimizationLSI LOGIC CORP·Filed 2002·Granted Oct 26, 2004·12 cites·18 claims
- 1267US6701493B2Floor plan tester for integrated circuit designLSI LOGIC CORP·Filed 2002·Granted Mar 2, 2004·12 cites·14 claims
- 1367US6637011B1Method and apparatus for quick search for identities applicable to specified formulaLSI LOGIC CORP·Filed 2000·Granted Oct 21, 2003·13 cites·18 claims
- 1466US7496870B2Method of selecting cells in logic restructuringLSI CORP·Filed 2006·Granted Feb 24, 2009·3 cites·16 claims
- 1564US6470487B1Parallelization of resynthesisLSI LOGIC CORP·Filed 2001·Granted Oct 22, 2002·10 cites·9 claims
- 1659US6868536B2Method to find boolean function symmetriesLSI LOGIC CORP·Filed 2002·Granted Mar 15, 2005·6 cites·15 claims
- 1754US7398486B2Method and apparatus for performing logical transformations for global routingLSI CORP·Filed 2004·Granted Jul 8, 2008·4 cites·8 claims
- 1852US7257791B2Multiple buffer insertion in global routingLSI CORP·Filed 2004·Granted Aug 14, 2007·3 cites·20 claims
- 1952US6553551B1Timing recomputationLSI LOGIC CORP·Filed 2001·Granted Apr 22, 2003·2 cites·11 claims
- 2051US7568175B2Ramptime propagation on designs with cyclesLSI CORP·Filed 2007·Granted Jul 28, 2009·0 cites·5 claims
- 2150US6701503B2Overlap remover managerLSI LOGIC CORP·Filed 2002·Granted Mar 2, 2004·1 cites·35 claims
- 2249US7146591B2Method of selecting cells in logic restructuringLSI LOGIC CORP·Filed 2004·Granted Dec 5, 2006·1 cites·6 claims
- 2348US7246336B2Ramptime propagation on designs with cyclesLSI CORP·Filed 2004·Granted Jul 17, 2007·0 cites·15 claims
- 2445US7111267B2Process and apparatus to assign coordinates to nodes of logical trees without increase of wire lengthsLSI LOGIC CORP·Filed 2004·Granted Sep 19, 2006·0 cites·20 claims
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