Inventor · disambiguated record
Aiguo Lu
Also filed as: LU AIGUO
22 granted patents·396 citations·filing 2000–2013
96Inventor score
Top patents by PatentIndex Score
22 records- 0190US6550045B1Changing clock delays in an integrated circuit for skew optimizationLSI LOGIC CORP·Filed 2001·Granted Apr 15, 2003·88 cites·16 claims
- 0289US6550044B1Method in integrating clock tree synthesis and timing optimization for an integrated circuit designLSI LOGIC CORP·Filed 2001·Granted Apr 15, 2003·59 cites·9 claims
- 0387US6546541B1Placement-based integrated circuit re-synthesis tool using estimated maximum interconnect capacitancesLSI LOGIC CORP·Filed 2001·Granted Apr 8, 2003·52 cites·20 claims
- 0484US7356785B2Optimizing IC clock structures by minimizing clock uncertaintyLSI LOGIC CORP·Filed 2006·Granted Apr 8, 2008·11 cites·5 claims
- 0582US8516425B2Method and computer program for generating grounded shielding wires for signal wiringNIKITIN ANDREY·Filed 2012·Granted Aug 20, 2013·7 cites·25 claims
- 0681US9460258B2Shaping integrated with power network synthesis (PNS) for power grid (PG) alignmentSYNOPSYS INC·Filed 2013·Granted Oct 4, 2016·7 cites·18 claims
- 0779US6637016B1Assignment of cell coordinatesLSI LOGIC CORP·Filed 2001·Granted Oct 21, 2003·27 cites·13 claims
- 0877US6487697B1Distribution dependent clustering in buffer insertion of high fanout netsLSI LOGIC CORP·Filed 2001·Granted Nov 26, 2002·24 cites·21 claims
- 0975US7996804B2Signal delay skew reduction systemLSI CORP·Filed 2008·Granted Aug 9, 2011·6 cites·15 claims
- 1075US7096442B2Optimizing IC clock structures by minimizing clock uncertaintyLSI LOGIC CORP·Filed 2003·Granted Aug 22, 2006·18 cites·14 claims
- 1171US6629304B1Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cellsLSI LOGIC CORP·Filed 2001·Granted Sep 30, 2003·16 cites·25 claims
- 1271US6557144B1Netlist resynthesis program based on physical delay calculationLSI LOGIC CORP·Filed 2000·Granted Apr 29, 2003·16 cites·7 claims
- 1367US6810515B2Process of restructuring logics in ICs for setup and hold time optimizationLSI LOGIC CORP·Filed 2002·Granted Oct 26, 2004·12 cites·18 claims
- 1467US6701493B2Floor plan tester for integrated circuit designLSI LOGIC CORP·Filed 2002·Granted Mar 2, 2004·12 cites·14 claims
- 1564US6470487B1Parallelization of resynthesisLSI LOGIC CORP·Filed 2001·Granted Oct 22, 2002·10 cites·9 claims
- 1661US8239813B2Method and apparatus for balancing signal delay skewNIKITIN ANDREY·Filed 2011·Granted Aug 7, 2012·1 cites·17 claims
- 1761US7243324B2Method of buffer insertion to achieve pin specific delaysLSI CORP·Filed 2005·Granted Jul 10, 2007·2 cites·18 claims
- 1859US6934733B1Optimization of adder based circuit architectureLSI LOGIC CORP·Filed 2001·Granted Aug 23, 2005·8 cites·20 claims
- 1959US6868536B2Method to find boolean function symmetriesLSI LOGIC CORP·Filed 2002·Granted Mar 15, 2005·6 cites·15 claims
- 2058US6691283B1Optimization of comparator architectureLSI LOGIC CORP·Filed 2001·Granted Feb 10, 2004·7 cites·21 claims
- 2157US6463572B1IC timing analysis with known false pathsLSI LOGIC CORP·Filed 2001·Granted Oct 8, 2002·5 cites·19 claims
- 2252US6553551B1Timing recomputationLSI LOGIC CORP·Filed 2001·Granted Apr 22, 2003·2 cites·11 claims
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