Inventor · disambiguated record
Michael D. Hutton
Also filed as: HUTTON MICHAEL · HUTTON MICHAEL D · HUTTON MICHAEL DAVID
113 granted patents·6 pending applications·1,720 citations·filing 2000–2025
99Inventor score
Top patents by PatentIndex Score
119 records- 0198US9106229B1Programmable interposer circuitryALTERA CORP·Filed 2013·Granted Aug 11, 2015·187 cites·21 claims
- 0298US7420390B1Method and apparatus for implementing additional registers in field programmable gate arrays to reduce design sizeALTERA CORP·Filed 2006·Granted Sep 2, 2008·61 cites·37 claims
- 0398US7135888B1Programmable routing structures providing shorter timing delays for input/output signalsALTERA CORP·Filed 2004·Granted Nov 14, 2006·179 cites·19 claims
- 0498US6407576B1Interconnection and input/output resources for programmable logic integrated circuit devicesALTERA CORP·Filed 2000·Granted Jun 18, 2002·183 cites·41 claims
- 0597US9697318B2State visibility and manipulation in integrated circuitsALTERA CORP·Filed 2015·Granted Jul 4, 2017·26 cites·20 claims
- 0697US8314636B2Field programmable gate array with integrated application specific integrated circuit fabricHUTTON MICHAEL D·Filed 2010·Granted Nov 20, 2012·28 cites·21 claims
- 0797US7120883B1Register retiming techniqueALTERA CORP·Filed 2003·Granted Oct 10, 2006·129 cites·6 claims
- 0895US9450609B1Methods and apparatus for embedding an error correction code in memory cellsALTERA CORP·Filed 2015·Granted Sep 20, 2016·13 cites·25 claims
- 0995US9294092B2Error resilient packaged componentsALTERA CORP·Filed 2013·Granted Mar 22, 2016·15 cites·19 claims
- 1095US8542032B1Integrated circuits with interconnect selection circuitryHUTTON MICHAEL D·Filed 2012·Granted Sep 24, 2013·13 cites·21 claims
- 1195US8072238B1Programmable logic device architecture with the ability to combine adjacent logic elements for the purpose of performing high order logic functionsHUTTON MICHAEL D·Filed 2010·Granted Dec 6, 2011·17 cites·23 claims
- 1294US9053274B1Register retiming techniqueALTERA CORP·Filed 2014·Granted Jun 9, 2015·14 cites·17 claims
- 1394US8704548B1Methods and apparatus for building bus interconnection networks using programmable interconnection resourcesALTERA CORP·Filed 2012·Granted Apr 22, 2014·12 cites·22 claims
- 1494US7818705B1Method and apparatus for implementing a field programmable gate array architecture with programmable clock skewALTERA CORP·Filed 2005·Granted Oct 19, 2010·33 cites·18 claims
- 1594US7689955B1Register retiming techniqueALTERA CORP·Filed 2006·Granted Mar 30, 2010·28 cites·20 claims
- 1694US7337100B1Physical resynthesis of a logic designALTERA CORP·Filed 2003·Granted Feb 26, 2008·142 cites·39 claims
- 1793US9479456B2Programmable logic device with integrated network-on-chipALTERA CORP·Filed 2013·Granted Oct 25, 2016·15 cites·20 claims
- 1893US8402408B1Register retiming techniqueVAN ANTWERPEN BABETTE·Filed 2011·Granted Mar 19, 2013·19 cites·20 claims
- 1992US9798842B1Circuit design instrumentation for state visualizationALTERA CORP·Filed 2015·Granted Oct 24, 2017·9 cites·20 claims
- 2092US7902864B1Heterogeneous labsALTERA CORP·Filed 2005·Granted Mar 8, 2011·22 cites·45 claims
- 2192US6747480B1Programmable logic devices with bidirect ional cascadesALTERA CORP·Filed 2002·Granted Jun 8, 2004·46 cites·16 claims
- 2291US9178513B1Memory blocks with shared address bus circuitryALTERA CORP·Filed 2013·Granted Nov 3, 2015·10 cites·25 claims
- 2391US8108812B1Register retiming techniqueVAN ANTWERPEN BABETTE·Filed 2010·Granted Jan 31, 2012·12 cites·20 claims
- 2490US8381142B1Using a timing exception to postpone retimingALTERA CORP·Filed 2007·Granted Feb 19, 2013·23 cites·19 claims
- 2589US9077338B1Method and circuit for scalable cross point switching using 3-D die stackingALTERA CORP·Filed 2014·Granted Jul 7, 2015·10 cites·20 claims
- 2689US7812635B1Programmable logic device architecture with the ability to combine adjacent logic elements for the purpose of performing high order logic functionsALTERA CORP·Filed 2006·Granted Oct 12, 2010·15 cites·20 claims
- 2789US7705628B1Programmable logic device having logic elements with dedicated hardware to configure look up tables as registersALTERA CORP·Filed 2006·Granted Apr 27, 2010·13 cites·24 claims
- 2889US7469394B1Timing variation aware compilationALTERA CORP·Filed 2006·Granted Dec 23, 2008·29 cites·37 claims
- 2988US10635631B2Hybrid programmable many-core device with on-chip interconnectALTERA CORP·Filed 2018·Granted Apr 28, 2020·4 cites·25 claims
- 3088US7671625B1Omnibus logic elementALTERA CORP·Filed 2008·Granted Mar 2, 2010·10 cites·20 claims
- 3187US10523207B2Programmable circuit having multiple sectorsALTERA CORP·Filed 2014·Granted Dec 31, 2019·6 cites·18 claims
- 3287US9588176B1Techniques for using scan storage circuitsALTERA CORP·Filed 2015·Granted Mar 7, 2017·9 cites·31 claims
- 3387US7492188B2Interconnection and input/output resources for programmable logic integrated circuit devicesALTERA CORP·Filed 2007·Granted Feb 17, 2009·9 cites·22 claims
- 3486US9165931B1Apparatus for field-programmable gate array with configurable architecture and associated methodsSCHMIT HERMAN·Filed 2014·Granted Oct 20, 2015·6 cites·20 claims
- 3586US8082526B2Dedicated crossbar and barrel shifter block on programmable logic resourcesHUTTON MICHAEL·Filed 2008·Granted Dec 20, 2011·18 cites·20 claims
- 3686US7784008B1Performance visualization systemALTERA CORP·Filed 2006·Granted Aug 24, 2010·20 cites·25 claims
- 3785US9575862B1Integrated circuits with error handling capabilitiesALTERA CORP·Filed 2014·Granted Feb 21, 2017·16 cites·20 claims
- 3885US7394287B1Programmable logic device having complex logic blocks with improved logic cell functionalityALTERA CORP·Filed 2007·Granted Jul 1, 2008·11 cites·23 claims
- 3985US7330052B2Area efficient fractureable logic elementsALTERA CORP·Filed 2005·Granted Feb 12, 2008·13 cites·23 claims
- 4084US9583218B1Configurable register circuitry for error detection and recoveryALTERA CORP·Filed 2014·Granted Feb 28, 2017·7 cites·21 claims
- 4184US7042248B1Dedicated crossbar and barrel shifter block on programmable logic resourcesALTERA CORP·Filed 2003·Granted May 9, 2006·31 cites·15 claims
- 4283US9478272B1Configurable storage blocks with embedded first-in first-out and last-in first-out circuitryALTERA CORP·Filed 2014·Granted Oct 25, 2016·8 cites·31 claims
- 4383US8806399B1Register retiming techniqueALTERA CORP·Filed 2013·Granted Aug 12, 2014·4 cites·20 claims
- 4482US7545196B1Clock distribution for specialized processing block in programmable logic deviceALTERA CORP·Filed 2006·Granted Jun 9, 2009·12 cites·26 claims
- 4581US8185854B1Method and apparatus for performing parallel slack computation within a shared netlist regionHUTTON MICHAEL D·Filed 2009·Granted May 22, 2012·11 cites·32 claims
- 4681US8112728B1Early timing estimation of timing statistical properties of placementHUTTON MICHAEL D·Filed 2009·Granted Feb 7, 2012·9 cites·19 claims
- 4781US7827433B1Time-multiplexed routing for reducing pipelining registersALTERA CORP·Filed 2007·Granted Nov 2, 2010·10 cites·23 claims
- 4880US7607118B1Techniques for using edge masks to perform timing analysisALTERA CORP·Filed 2006·Granted Oct 20, 2009·8 cites·60 claims
- 4979US9251300B2Methods and tools for designing integrated circuits with auto-pipelining capabilitiesALTERA CORP·Filed 2013·Granted Feb 2, 2016·7 cites·28 claims
- 5079US7724032B2Field programmable gate array with integrated application specific integrated circuit fabricALTERA CORP·Filed 2007·Granted May 25, 2010·7 cites·17 claims
Showing the top 50 of 119 patent records by PatentIndex Score.
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