Inventor

LESARTRE GREGG B

US75 patents

⚠️ This page may combine multiple inventors who share the name “LESARTRE GREGG B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LESARTRE GREGG B

HEWLETT PACKARD ENTPR DEV LP

Iterative write sequence interrupt

Live migration of data

Saving position of a wear level rotation

Re-encoding data associated with failed memory devices

Virtual channel routing

Transmitter that does not resend a packet despite receipt of a message to resend the packet

Utilization of component group tables in a computing network

Systems and methods for restricting write access to non-volatile memory

Serializing access to fault tolerant memory

Adjusting memory parameters

Network congestion management

Masterless raid for byte-addressable non-volatile memory

Transaction request epochs

Transmitting contents of an operation field to a media controller

Retrieve data block from determined devices

Serializing access to fault tolerant memory

Data sensing in crosspoint memory structures

Multi-tier security framework

Data write to subset of memory devices

Detection of error patterns in memory dies

Rendering data invalid in a memory array

Error correction code in memory

Write tracking for memories

Age class based arbitration

Memory location remapping and wear-levelling

Device supporting ordered and unordered transaction classes

Split mode addressing a persistent memory

External memory controller

Side cache

HEWLETT PACKARD CO

Circuitry for providing external access to signals that are internal to an integrated circuit chip package

Method for processing information in a microprocessor to facilitate debug and performance monitoring

System and method for on-chip debug support and performance monitoring in a microprocessor

Cache line replacement using cache status to bias way selection

Flexible circuitry and method for detecting signal patterns on a bus

Cache line replacement using cable status to bias way selection

Apparatus and method for tracking events in a microprocessor that can retire more than one instruction during a clock cycle

Apparatus and method for reading and writing remote registers on an integrated circuit chip using a minimum of interconnects

Speculative pre-flush of data in an out-of-order execution processor system

Method and system for recovering from cache misses

Operand dependency tracking system and method for a processor that executes instructions out of order

HEWLETT PACKARD DEVELOPMENT CO

Speculative pre-fetching additional line on cache miss if no request pending in out-of-order processor

Memory device having error correction logic

Method and apparatus for saving microprocessor power when sequentially accessing the microprocessor&#39;s instruction cache

External memory controller

Method and apparatus for loopback self testing

Link training for a serdes link

Hardware method for implementing atomic semaphore operations using code macros

Non-volatile memory to store resettable data

LESARTRE GREGG B

Managing latencies in a multiprocessor interconnect

Systems and methods for resource access

Method and apparatus for saving microprocessor power when sequentially accessing the microprocessor's instruction cache