Inventor · disambiguated record
Andreas Sembrant
Also filed as: SEMBRANT ANDREAS · SEMBRANT ANDREAS KARL
14 granted patents·1 pending application·25 citations·filing 2014–2024
88Inventor score
Top patents by PatentIndex Score
15 records- 0193US10019368B2Placement policy for memory hierarchiesSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Jul 10, 2018·10 cites·42 claims
- 0290US11138121B2Systems and methods for efficient cacheline handling based on predictionsSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Oct 5, 2021·8 cites·13 claims
- 0386US11615026B2Systems and methods for implementing coherent memory in a multiprocessor systemSAMSUNG ELECTRONICS CO LTD·Filed 2022·Granted Mar 28, 2023·1 cites·20 claims
- 0479US10713166B2Efficient early ordering mechanismSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Jul 14, 2020·2 cites·20 claims
- 0575US10402344B2Systems and methods for direct data access in multi-level cache memory hierarchiesSAMSUNG ELECTRONICS CO LTD·Filed 2014·Granted Sep 3, 2019·3 cites·28 claims
- 0669US10866891B2Systems and methods for efficient compressed cache line storage and handlingSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Dec 15, 2020·1 cites·20 claims
- 0767US11237969B2Systems and methods for implementing coherent memory in a multiprocessor systemSAMSUNG ELECTRONICS CO LTD·Filed 2020·Granted Feb 1, 2022·0 cites·20 claims
- 0862US11354242B2Efficient early ordering mechanismSAMSUNG ELECTRONICS CO LTD·Filed 2020·Granted Jun 7, 2022·0 cites·20 claims
- 0955US10671543B2Systems and methods for reducing first level cache energy by eliminating cache address tagsSAMSUNG ELECTRONICS CO LTD·Filed 2014·Granted Jun 2, 2020·0 cites·15 claims
- 1055US10031849B2Tracking alternative cacheline placement locations in a cache hierarchySAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Jul 24, 2018·0 cites·40 claims
- 1154US10402331B2Systems and methods for implementing a tag-less shared cache and a larger backing cacheSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Sep 3, 2019·0 cites·17 claims
- 1252US10754777B2Systems and methods for implementing coherent memory in a multiprocessor systemSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Aug 25, 2020·0 cites·20 claims
- 1350US10884925B2Systems and methods for tag-less buffer implementationSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Jan 5, 2021·0 cites·20 claims
- 1450US10409725B2Management of shared pipeline resource usage based on level informationSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Sep 10, 2019·0 cites·26 claims
- 1549US2025291873A1Universal Scale Metadata Layout for Matrix Multiply and Add (MMA)NVDIA CORP·Filed 2024·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →