Inventor · disambiguated record
Fabiano Peixoto
Also filed as: PEIXOTO FABIANO · PEIXOTO FABIANO CRUZ
10 granted patents·53 citations·filing 2011–2019
87Inventor score
Technology areasG06F
Top patents by PatentIndex Score
10 records- 0189US10204201B1Methods, systems, and articles of manufacture for verifying an electronic design using hierarchical clock domain crossing verification techniquesCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Feb 12, 2019·12 cites·21 claims
- 0287US8572527B1Generating properties for circuit designsCOELHO JR CLAUDIONOR JOSE NUNES·Filed 2011·Granted Oct 29, 2013·18 cites·28 claims
- 0384US10162917B1Method and system for implementing selective transformation for low power verificationCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Dec 25, 2018·5 cites·21 claims
- 0481US9633151B1Methods, systems, and computer program product for verifying electronic designs with clock domain crossing pathsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Apr 25, 2017·5 cites·20 claims
- 0576US9817930B1Method, system, and computer program product for verifying an electronic circuit design with a graph-based proof flowCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Nov 14, 2017·6 cites·21 claims
- 0671US9665682B1Methods, systems, and articles of manufacture for enhancing formal verification with counter acceleration for electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted May 30, 2017·2 cites·20 claims
- 0767US10796051B1Adaptive model interface for a plurality of EDA programsCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Oct 6, 2020·2 cites·20 claims
- 0866US10540467B1System, method, and computer program product for handling combinational loops associated with the formal verification of an electronic circuit designCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Jan 21, 2020·1 cites·20 claims
- 0956US10769008B1Systems and methods for automatic formal metastability fault analysis in an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Sep 8, 2020·1 cites·12 claims
- 1052US10078714B2Data propagation analysis for debugging a circuit designPEIXOTO FABIANO·Filed 2013·Granted Sep 18, 2018·1 cites·20 claims
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