Inventor · disambiguated record
Yarsun Hsu
Also filed as: HSU YARSUN
11 granted patents·358 citations·filing 1987–2008
92Inventor score
Top patents by PatentIndex Score
11 records- 0178US5822763ACache coherence protocol for reducing the effects of false sharing in non-bus-based shared-memory multiprocessorsIBM·Filed 1996·Granted Oct 13, 1998·89 cites·16 claims
- 0277US6094709ACache coherence for lazy entry consistency in lockup-free cachesIBM·Filed 1997·Granted Jul 25, 2000·87 cites·9 claims
- 0367US4851995AProgrammable variable-cycle clock circuit for skew-tolerant array processor architectureIBM·Filed 1987·Granted Jul 25, 1989·39 cites·15 claims
- 0466US8108762B2Operating method and circuit for low density parity check (LDPC) decoderLIU CHIH-HAO·Filed 2007·Granted Jan 31, 2012·7 cites·14 claims
- 0565US7719442B2Multi-mode multi-parallelism data exchange method and device thereofUNIV NAT CHIAO TUNG·Filed 2008·Granted May 18, 2010·5 cites·18 claims
- 0661US5287491ANetwork rearrangement method and systemIBM·Filed 1989·Granted Feb 15, 1994·24 cites·2 claims
- 0755US5778437AInvalidation bus optimization for multiprocessors using directory-based cache coherence protocols in which an address of a line to be modified is placed on the invalidation bus simultaneously with sending a modify request to the directoryIBM·Filed 1995·Granted Jul 7, 1998·31 cites·10 claims
- 0855US5046000ASingle-FIFO high speed combining switchIBM·Filed 1989·Granted Sep 3, 1991·22 cites·18 claims
- 0951US5313649ASwitch queue structure for one-network parallel processor systemsIBM·Filed 1991·Granted May 17, 1994·24 cites·4 claims
- 1049US6175899B1Method for providing virtual atomicity in multi processor environment having access to multilevel cachesIBM·Filed 1997·Granted Jan 16, 2001·23 cites·9 claims
- 1134US6148375AHierarchical bus simple COMA architecture for shared memory multiprocessors having a bus directly interconnecting caches between nodesIBM·Filed 1998·Granted Nov 14, 2000·7 cites·3 claims
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