Inventor · disambiguated record
Sridhar Begur
Also filed as: BEGUR SRIDHAR
11 granted patents·714 citations·filing 1990–2000
93Inventor score
Top patents by PatentIndex Score
11 records- 0189US5784649AMulti-threaded FIFO pool buffer and bus transfer control systemDIAMOND MULTIMEDIA SYSTEMS INC·Filed 1996·Granted Jul 21, 1998·197 cites·12 claims
- 0283US5797043ASystem for managing the transfer of data between FIFOs within pool memory and peripherals being programmable with identifications of the FIFOsDIAMOND MULTIMEDIA SYSTEMS INC·Filed 1996·Granted Aug 18, 1998·128 cites·10 claims
- 0382US6044225AMultiple parallel digital data stream channel controllerDIAMOND MULTIMEDIA SYSTEMS INC·Filed 1996·Granted Mar 28, 2000·119 cites·15 claims
- 0482US5822553AMultiple parallel digital data stream channel controller architectureDIAMOND MULTIMEDIA SYSTEMS INC·Filed 1996·Granted Oct 13, 1998·130 cites·18 claims
- 0578US6940807B1Method and apparatus for a X-DSL communication processorVELOCITY COMMUNICATION INC·Filed 2000·Granted Sep 6, 2005·31 cites·13 claims
- 0673US7028063B1Method and apparatus for a DFT/IDFT engine supporting multiple X-DSL protocolsVELOCITY COMMUNICATION INC·Filed 2000·Granted Apr 11, 2006·21 cites·16 claims
- 0750US5301328ASystem and method for shadowing and re-mapping reserved memory in a microcomputerHEWLETT PACKARD CO·Filed 1992·Granted Apr 5, 1994·23 cites·7 claims
- 0850US5202994ASystem and method for shadowing and re-mapping reserved memory in a microcomputerHEWLETT PACKARD CO·Filed 1990·Granted Apr 13, 1993·24 cites·15 claims
- 0943US6202120B1System and method for accessing data between a host bus and a system memory bus where the system memory bus has a data path that is twice the width of the data path for the host busHEWLETT PACKARD CO·Filed 1999·Granted Mar 13, 2001·15 cites·16 claims
- 1042US5732406AMicroprocessor burst mode with external system memoryHEWLETT PACKARD CO·Filed 1992·Granted Mar 24, 1998·15 cites·24 claims
- 1140US5960450ASystem and method for accessing data between a host bus and system memory buses in which each system memory bus has a data path which is twice the width of the data path for the host busHEWLETT PACKARD CO·Filed 1992·Granted Sep 28, 1999·11 cites·18 claims
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