Inventor · disambiguated record
Viktor Salitrennik
Also filed as: SALITRENNIK VIKTOR
8 granted patents·49 citations·filing 2005–2016
84Inventor score
Technology areasG06F
Top patents by PatentIndex Score
8 records- 0191US9372947B1Compacting trace data generated by emulation processors during emulation of a circuit designCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Jun 21, 2016·14 cites·20 claims
- 0287US9298866B1Method and system for modeling a flip-flop of a user designCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Mar 29, 2016·10 cites·20 claims
- 0385US9171111B1Hardware emulation method and system using a port time shift registerCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Oct 27, 2015·8 cites·18 claims
- 0479US7379861B2Dynamic programming of trigger conditions in hardware emulation systemsQUICKTURN DESIGN SYSTEMS INC·Filed 2005·Granted May 27, 2008·11 cites·25 claims
- 0576US8959010B1Emulation system with improved reliability of interconnect and a method for programming such interconnectBERSHTEYN MIKHAIL·Filed 2011·Granted Feb 17, 2015·5 cites·21 claims
- 0666US10509877B1Systems and methods for reducing latency when transferring I/O between an emulator and target deviceCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Dec 17, 2019·1 cites·20 claims
- 0754US9646120B1Method and system for trace compaction during emulation of a circuit designCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted May 9, 2017·0 cites·6 claims
- 0850US9292639B1Method and system for providing additional look-up tablesCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Mar 22, 2016·0 cites·20 claims
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