Inventor

NORDQUIST BRYON S

US26 patents

⚠️ This page may combine multiple inventors who share the name “NORDQUIST BRYON S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NORDQUIST BRYON S

NVIDIA CORP

Multithreaded SIMD parallel processor with launching of groups of threads

Apparatus, system, and method for coalescing parallel memory requests

Multithreaded SIMD parallel processor with loading of groups of threads

Parallel data processing systems and methods using cooperative thread arrays and SIMD instruction issue

Off-chip memory allocation for a unified shader

Off-chip out of order memory allocation for a unified shader

Off-chip memory allocation for a unified shader

On-the-fly reordering of multi-cycle data transfers

Linking texture headers and texture samplers

Distributing processing tasks within a processor

Virtual copying scheme for creating multiple versions of state information

Parallel copying scheme for creating multiple versions of state information

Technique for accessing content-addressable memory

On-the-fly reordering of 32-bit per component texture images in a multi-cycle data transfer

Load/store operations in texture hardware

Configurable state table for managing multiple versions of state information

Pixel stream assembly for raster operations

Technique for performing memory access operations via texture hardware

Technique for performing memory access operations via texture hardware

NORDQUIST BRYON S

Managing state information for a multi-threaded processor

Pixel shader program thread assembly

Off-chip out of order memory allocation for a unified shader

LINDHOLM JOHN ERIK

Thread-type-based load balancing in a multithreaded processor

Thread-type-based resource allocation in a multithreaded processor

DULUK JR JEROME F

Thread count throttling for efficient resource utilization

COON BRETT W

Soldier-on mode to control processor error handling behavior