Inventor · disambiguated record
Paul A. Hyde
Also filed as: HYDE PAUL A
11 granted patents·45 citations·filing 2003–2011
87Inventor score
Top patents by PatentIndex Score
11 records- 0190US7862233B2Self heating monitor for SiGe and SOI CMOS devicesIBM·Filed 2007·Granted Jan 4, 2011·12 cites·6 claims
- 0277US7406397B2Self heating monitor for SiGe and SOI CMOS devicesIBM·Filed 2004·Granted Jul 29, 2008·11 cites·32 claims
- 0375US7805274B2Structure and methodology for characterizing device self-heatingIBM·Filed 2006·Granted Sep 28, 2010·4 cites·18 claims
- 0466US8296691B2Methodology for improving device performance prediction from effects of active area corner roundingCHIDAMBARRAO DURESETI·Filed 2008·Granted Oct 23, 2012·4 cites·24 claims
- 0565US8392867B2System, method and program storage device for developing condensed netlists representative of groups of active devices in an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlistsDENG YANQING·Filed 2011·Granted Mar 5, 2013·4 cites·25 claims
- 0664US6861716B1Ladder-type gate structure for four-terminal SOI semiconductor deviceIBM·Filed 2003·Granted Mar 1, 2005·10 cites·12 claims
- 0751US8412487B2Self heating monitor for SiGe and SOI CMOS devicesHYDE PAUL A·Filed 2010·Granted Apr 2, 2013·0 cites·13 claims
- 0849US7979815B2Compact model methodology for PC landing pad lithographic rounding impact on device performanceIBM·Filed 2008·Granted Jul 12, 2011·0 cites·28 claims
- 0947US8302040B2Compact model methodology for PC landing pad lithographic rounding impact on device performanceCHIDAMBARRAO DURESETI·Filed 2011·Granted Oct 30, 2012·0 cites·5 claims
- 1042US8539426B2Method and system for extracting compact models for circuit simulationHYDE PAUL A·Filed 2011·Granted Sep 17, 2013·0 cites·23 claims
- 1138US7101745B2Method of forming ladder-type gate structure for four-terminal SOI semiconductor deviceIBM·Filed 2004·Granted Sep 5, 2006·0 cites·7 claims
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