Inventor · disambiguated record
Uri Leder
Also filed as: LEDER URI
13 granted patents·75 citations·filing 1984–2023
89Inventor score
Top patents by PatentIndex Score
13 records- 0196US10298496B1Packet processing cacheAMAZON TECH INC·Filed 2017·Granted May 21, 2019·32 cites·20 claims
- 0293US10228869B1Controlling shared resources and context dataAMAZON TECH INC·Filed 2017·Granted Mar 12, 2019·16 cites·21 claims
- 0392US11544436B1Hardware-software interaction testing using formal verificationAMAZON TECH INC·Filed 2021·Granted Jan 3, 2023·4 cites·20 claims
- 0488US10929584B1Environmental modification testing for design correctness with formal verificationAMAZON TECH INC·Filed 2019·Granted Feb 23, 2021·7 cites·20 claims
- 0588US10839124B1Interactive compilation of software to a hardware language to satisfy formal verification constraintsAMAZON TECH INC·Filed 2019·Granted Nov 17, 2020·7 cites·20 claims
- 0679US10911358B1Packet processing cacheAMAZON TECH INC·Filed 2019·Granted Feb 2, 2021·2 cites·20 claims
- 0770US11182103B1Dedicated communications cacheAMAZON TECH INC·Filed 2019·Granted Nov 23, 2021·1 cites·20 claims
- 0851US12175178B1Fuzzy scoreboardAMAZON TECH INC·Filed 2021·Granted Dec 24, 2024·0 cites·21 claims
- 0950US12306719B1Link down resilienceAMAZON TECH INC·Filed 2023·Granted May 20, 2025·0 cites·19 claims
- 1048US12271669B1Executing instruction sequences generated from software interactions as part of formal verification of a design under testAMAZON TECH INC·Filed 2022·Granted Apr 8, 2025·0 cites·20 claims
- 1146US12361195B1Extending cover properties in formal verification to generate failure traces that reach end-of-testAMAZON TECH INC·Filed 2021·Granted Jul 15, 2025·0 cites·20 claims
- 1246US11768990B1Interconnect flow graph for integrated circuit designAMAZON TECH INC·Filed 2021·Granted Sep 26, 2023·0 cites·18 claims
- 1341US4512505AConvertible platen for graphics plotterSANDERS ASSOCIATES INC·Filed 1984·Granted Apr 23, 1985·6 cites·2 claims
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