Inventor · disambiguated record
Lawrence Pileggi
Also filed as: PILEGGI LAWRENCE · PILEGGI LAWRENCE T · PILEGGI LAWRENCE THOMAS
33 granted patents·9 pending applications·935 citations·filing 1998–2017
98Inventor score
Files withUNIV CARNEGIE MELLON15MONTEREY DESIGN SYSTEMS INC5PDF SOLUTIONS INC4MONTEREY DESIGN SYSTEMS3PILEGGI LAWRENCE T3
Top patents by PatentIndex Score
42 records- 0198US7278118B2Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component featuresPDF SOLUTIONS INC·Filed 2005·Granted Oct 2, 2007·212 cites·31 claims
- 0292US8198655B1Regular pattern arrays for memory and logic on a semiconductor substratePILEGGI LAWRENCE T·Filed 2009·Granted Jun 12, 2012·35 cites·21 claims
- 0391US6286128B1Method for design optimization using logical and physical informationMONTEREY DESIGN SYSTEMS INC·Filed 1998·Granted Sep 4, 2001·202 cites·10 claims
- 0488US6961916B2Placement method for integrated circuit design using topo-clusteringSYNOPSYS INC·Filed 2002·Granted Nov 1, 2005·45 cites·7 claims
- 0587US8400066B1Magnetic logic circuits and systems incorporating samePILEGGI LAWRENCE T·Filed 2010·Granted Mar 19, 2013·13 cites·31 claims
- 0687US6442743B1Placement method for integrated circuit design using topo-clusteringMONTEREY DESIGN SYSTEMS·Filed 1998·Granted Aug 27, 2002·126 cites·13 claims
- 0786US8476925B2Magnetic switching cells and methods of making and operating sameZHU JIAN-GANG JIMMY·Filed 2010·Granted Jul 2, 2013·8 cites·3 claims
- 0886US7487486B2Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variationsCELIK MUSTAFA·Filed 2005·Granted Feb 3, 2009·18 cites·8 claims
- 0985US7945868B2Tunable integrated circuit design for nano-scale technologiesUNIV CARNEGIE MELLON·Filed 2008·Granted May 17, 2011·12 cites·47 claims
- 1083US7634248B2Configurable circuits using phase change switchesUNIV CARNEGIE MELLON·Filed 2006·Granted Dec 15, 2009·13 cites·23 claims
- 1183US7096174B2Systems, methods and computer program products for creating hierarchical equivalent circuit modelsUNIV CARNEGIE MELLON·Filed 2001·Granted Aug 22, 2006·42 cites·57 claims
- 1279US9300301B2Nonvolatile magnetic logic deviceUNIV CARNEGIE MELLON·Filed 2013·Granted Mar 29, 2016·7 cites·32 claims
- 1377US8271916B2Method for the definition of a library of application-domain-specific logic cellsMOTIANI DIPTI·Filed 2010·Granted Sep 18, 2012·5 cites·44 claims
- 1476US7757187B2Method for mapping a Boolean logic network to a limited set of application-domain specific logic cellsPDF SOLUTIONS INC·Filed 2007·Granted Jul 13, 2010·7 cites·7 claims
- 1574US6820245B2Methods, systems, and computer program products for modeling inductive effects in a circuit by combining a plurality of localized modelsUNIV CARNEGIE MELLON·Filed 2002·Granted Nov 16, 2004·20 cites·47 claims
- 1672US10026431B2Magnetic shift registerUNIV CARNEGIE MELLON·Filed 2014·Granted Jul 17, 2018·2 cites·23 claims
- 1769US7908131B1Method for parameterized model order reduction of integrated circuit interconnectsUNIV CARNEGIE MELLON·Filed 2006·Granted Mar 15, 2011·4 cites·20 claims
- 1869US7906254B2Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component featuresPDF SOLUTIONS INC·Filed 2007·Granted Mar 15, 2011·3 cites·13 claims
- 1968US7325180B2System and method to test integrated circuits on a waferUNIV CARNEGIE MELLON·Filed 2003·Granted Jan 29, 2008·17 cites·58 claims
- 2065US9286216B23DIC memory chips including computational logic-in-memory for performing accelerated data processingUNIV CARNEGIE MELLON·Filed 2014·Granted Mar 15, 2016·2 cites·31 claims
- 2164US9117523B1Chainlink memoryMORRIS DANIEL H·Filed 2012·Granted Aug 25, 2015·5 cites·26 claims
- 2264US7350164B2Optimization and design method for configurable analog circuits and devicesUNIV CARNEGIE MELLON·Filed 2004·Granted Mar 25, 2008·9 cites·36 claims
- 2364US6775808B1Method and apparatus for generating sign-off prototypes for the design and fabrication of integrated circuitsMONTEREY DESIGN SYSTEMS INC·Filed 2000·Granted Aug 10, 2004·13 cites·34 claims
- 2462US7784013B2Method for the definition of a library of application-domain-specific logic cellsPDF Acquisition Corp·Filed 2007·Granted Aug 24, 2010·3 cites·62 claims
- 2559US6651232B1Method and system for progressive clock tree or mesh construction concurrently with physical designMONTEREY DESIGN SYSTEMS INC·Filed 1998·Granted Nov 18, 2003·35 cites·66 claims
- 2656US7827516B1Method and system for grouping logic in an integrated circuit design to minimize number of transistors and number of unique geometry patternsPDF SOLUTIONS INC·Filed 2008·Granted Nov 2, 2010·1 cites·18 claims
- 2754US6367051B1System and method for concurrent buffer insertion and placement of logic gatesMONTEREY DESIGN SYSTEMS INC·Filed 1998·Granted Apr 2, 2002·31 cites·23 claims
- 2849US8589833B2Method for the definition of a library of application-domain-specific logic cellsMOTIANI DIPTI·Filed 2012·Granted Nov 19, 2013·0 cites·12 claims
- 2949US6192508B1Method for logic optimization for improving timing and congestion during placement in integrated circuit designMONTEREY DESIGN SYSTEMS·Filed 1998·Granted Feb 20, 2001·23 cites·18 claims
- 3047US2010162193A1Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component featuresPILEGGI LAWRENCE T·Filed 2010·Application pending·0 cites
- 3147US2005065763A1Methods, systems, and computer program products for modeling inductive effects in a circuit by combining a plurality of localized modelsFiled 2004·Application pending·0 cites
- 3246US2005021319A1Methods, systems, and computer program products for modeling nonlinear systemsFiled 2004·Application pending·0 cites
- 3345US9524767B2Bitcell wth magnetic switching elementsUNIV CARNEGIE MELLON·Filed 2014·Granted Dec 20, 2016·0 cites·29 claims
- 3444US10393796B2Testing integrated circuits during split fabricationUNIV CARNEGIE MELLON·Filed 2015·Granted Aug 27, 2019·0 cites·20 claims
- 3543US2003046045A1Method and apparatus for analysing and modeling of analog systemsFiled 2002·Application pending·0 cites
- 3642US2011050281A1Method and system for grouping logic in an integrated circuit design to minimize number of transistors and number of unique geometry patternsMOE MATTHEW D·Filed 2010·Application pending·0 cites
- 3739US6449756B1Method for accurate and efficient updates of timing information logic synthesis, placement and routing for integrated circuit designMONTEREY DESIGN SYSTEMS·Filed 1998·Granted Sep 10, 2002·13 cites·23 claims
- 3838US2007019447A1Active resistors for reduction of transient power grid noiseUNIV CARNEGIE MELLON·Filed 2005·Application pending·0 cites
- 3937US6385760B2System and method for concurrent placement of gates and associated wiringMONTEREY DESIGN SYSTEMS INC·Filed 1998·Granted May 7, 2002·9 cites·8 claims
- 4034US2018158152A1Methods and Software for Calculating Optimal Power Flow in an Electrical Power Grid and Utilizations of SameUNIV CARNEGIE MELLON·Filed 2017·Application pending·0 cites
- 4133US2017184640A1Systems, Methods, and Software for Planning, Simulating, and Operating Electrical Power SystemsUNIV CARNEGIE MELLON·Filed 2017·Application pending·0 cites
- 4233US2016125288A1Physically Unclonable Functions Using Neuromorphic NetworksCARNEGIE MELLON UNIVERSITY A PENNSYLVANIA NON PROFIT CORP·Filed 2015·Application pending·0 cites
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