Inventor · disambiguated record
Richard S. Wise
Also filed as: WISE RICHARD · WISE RICHARD S · WISE RICHARD STEPHEN
93 granted patents·21 pending applications·1,038 citations·filing 1997–2019
99Inventor score
Top patents by PatentIndex Score
114 records- 0198US7859013B2Metal oxide field effect transistor with a sharp haloIBM·Filed 2007·Granted Dec 28, 2010·100 cites·17 claims
- 0296US8426300B2Self-aligned contact for replacement gate devicesRAMACHANDRAN RAVIKUMAR·Filed 2010·Granted Apr 23, 2013·49 cites·12 claims
- 0396US7476578B1Process for finFET spacer formationIBM·Filed 2007·Granted Jan 13, 2009·51 cites·6 claims
- 0495US7288482B2Silicon nitride etching methodsIBM·Filed 2005·Granted Oct 30, 2007·260 cites·18 claims
- 0594US9530665B2Protective trench layer and gate spacer in finFET devicesIBM·Filed 2014·Granted Dec 27, 2016·15 cites·10 claims
- 0692US9412654B1Graphene sacrificial deposition layer on beol copper liner-seed for mitigating queue-time issues between liner and plating stepIBM·Filed 2015·Granted Aug 9, 2016·9 cites·20 claims
- 0790US8018005B2CMOS (complementary metal oxide semiconductor) devices having metal gate NFETs and poly-silicon gate PFETsIBM·Filed 2010·Granted Sep 13, 2011·11 cites·9 claims
- 0889US9431395B2Protection of semiconductor-oxide-containing gate dielectric during replacement gate formationIBM·Filed 2014·Granted Aug 30, 2016·7 cites·10 claims
- 0989US7892928B2Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacersIBM·Filed 2007·Granted Feb 22, 2011·12 cites·28 claims
- 1089US7691701B1Method of forming gate stack and structure thereofIBM·Filed 2009·Granted Apr 6, 2010·16 cites·27 claims
- 1188US8759172B2Etch stop layer formation in metal gate processLI ZHENGWEN·Filed 2012·Granted Jun 24, 2014·7 cites·11 claims
- 1287US9391020B2Interconnect structure having large self-aligned viasST MICROELECTRONICS INC·Filed 2014·Granted Jul 12, 2016·7 cites·18 claims
- 1387US7943457B2Dual metal and dual dielectric integration for metal high-k FETsIBM·Filed 2009·Granted May 17, 2011·13 cites·15 claims
- 1486US8008160B2Method and structure for forming trench DRAM with asymmetric strapIBM·Filed 2008·Granted Aug 30, 2011·11 cites·17 claims
- 1585US8507375B1Alignment tolerant semiconductor contact and methodLABONTE ANDRE P·Filed 2012·Granted Aug 13, 2013·8 cites·16 claims
- 1685US7498271B1Nitrogen based plasma process for metal gate MOS deviceIBM·Filed 2008·Granted Mar 3, 2009·10 cites·2 claims
- 1784US9214541B2Self-aligned contact for replacement gate devicesGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 15, 2015·6 cites·20 claims
- 1883US7671421B2CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materialsIBM·Filed 2006·Granted Mar 2, 2010·8 cites·13 claims
- 1983US6869542B2Hard mask integrated etch process for patterning of silicon oxide and other dielectric materialsIBM·Filed 2003·Granted Mar 22, 2005·35 cites·17 claims
- 2083US6838347B1Method for reducing line edge roughness of oxide material using chemical oxide removalIBM·Filed 2003·Granted Jan 4, 2005·28 cites·12 claims
- 2183US6541320B2Method to controllably form notched polysilicon gate structuresIBM·Filed 2001·Granted Apr 1, 2003·32 cites·24 claims
- 2282US9236447B2Asymmetric spacersIBM·Filed 2015·Granted Jan 12, 2016·3 cites·9 claims
- 2382US8435891B2Converting metal mask to metal-oxide etch stop layer and related semiconductor structureENGEL BRETT H·Filed 2011·Granted May 7, 2013·6 cites·17 claims
- 2481US9659820B2Interconnect structure having large self-aligned viasIBM·Filed 2016·Granted May 23, 2017·3 cites·9 claims
- 2581US8158481B2CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materialsCHEN TZE-CHIANG·Filed 2010·Granted Apr 17, 2012·5 cites·8 claims
- 2680US9214429B2Trench interconnect having reduced fringe capacitanceST MICROELECTRONICS INC·Filed 2013·Granted Dec 15, 2015·5 cites·20 claims
- 2780US8586431B2Three dimensional integration and methods of through silicon via creationIBM·Filed 2013·Granted Nov 19, 2013·3 cites·10 claims
- 2880US8492252B2Three dimensional integration and methods of through silicon via creationFAROOQ MUKTA G·Filed 2012·Granted Jul 23, 2013·3 cites·6 claims
- 2979US9691900B2Dual epitaxy CMOS processing using selective nitride formation for reduced gate pitchIBM·Filed 2014·Granted Jun 27, 2017·3 cites·17 claims
- 3079US9577068B2Protection of semiconductor-oxide-containing gate dielectric during replacement gate formationIBM·Filed 2016·Granted Feb 21, 2017·2 cites·17 claims
- 3179US9080239B2Method and apparatus for angular high density plasma chemical vapor depositionYANG DAEWON·Filed 2012·Granted Jul 14, 2015·4 cites·11 claims
- 3278US8415238B2Three dimensional integration and methods of through silicon via creationFAROOQ MUKTA G·Filed 2010·Granted Apr 9, 2013·3 cites·4 claims
- 3377US7329602B2Wiring structure for integrated circuit with reduced intralevel capacitanceIBM·Filed 2005·Granted Feb 12, 2008·6 cites·16 claims
- 3477US6345399B1Hard mask process to prevent surface roughness for selective dielectric etchingIBM·Filed 2000·Granted Feb 12, 2002·20 cites·17 claims
- 3576US8436427B2Dual metal and dual dielectric integration for metal high-K FETsCHUDZIK MICHAEL P·Filed 2011·Granted May 7, 2013·4 cites·20 claims
- 3676US7919379B2Dielectric spacer removalIBM·Filed 2007·Granted Apr 5, 2011·5 cites·14 claims
- 3775US10325998B2High selectivity nitride removal process based on selective polymer depositionIBM·Filed 2017·Granted Jun 18, 2019·1 cites·11 claims
- 3875US10269924B2High selectivity nitride removal process based on selective polymer depositionIBM·Filed 2017·Granted Apr 23, 2019·1 cites·7 claims
- 3975US8030157B1Liner protection in deep trench etchingIBM·Filed 2010·Granted Oct 4, 2011·4 cites·8 claims
- 4074US8569154B2Three dimensional integration and methods of through silicon via creationFAROOQ MUKTA G·Filed 2012·Granted Oct 29, 2013·2 cites·7 claims
- 4174US8287980B2Edge protection seal for bonded substratesFAROOQ MUKTA G·Filed 2009·Granted Oct 16, 2012·3 cites·22 claims
- 4274US8193099B1Protecting exposed metal gate structures from etching processes in integrated circuit manufacturingKHARE MUKESH V·Filed 2011·Granted Jun 5, 2012·4 cites·20 claims
- 4374US6355567B1Retrograde openings in thin filmsIBM·Filed 1999·Granted Mar 12, 2002·42 cites·10 claims
- 4473US8829612B2Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacersCHENG KANGGUO·Filed 2011·Granted Sep 9, 2014·2 cites·23 claims
- 4573US8580628B2Integrated circuit contact structure and methodLABONTE ANDRE P·Filed 2012·Granted Nov 12, 2013·4 cites·11 claims
- 4673US8399180B2Three dimensional integration with through silicon vias having multiple diametersFAROOQ MUKTA G·Filed 2010·Granted Mar 19, 2013·3 cites·11 claims
- 4772US9709898B2Amplification method for photoresist exposure in semiconductor chip manufacturingIBM·Filed 2014·Granted Jul 18, 2017·1 cites·18 claims
- 4871US8492280B1Method for simultaneously forming features of different depths in a semiconductor substrateHICHRI HABIB·Filed 2012·Granted Jul 23, 2013·3 cites·15 claims
- 4970US9627533B2High selectivity nitride removal process based on selective polymer depositionIBM·Filed 2015·Granted Apr 18, 2017·1 cites·10 claims
- 5070US8785281B2CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materialsCHEN TZE-CHIANG·Filed 2012·Granted Jul 22, 2014·2 cites·20 claims
Showing the top 50 of 114 patent records by PatentIndex Score.
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