Inventor · disambiguated record
Paul D Nuber
Also filed as: NUBER PAUL · NUBER PAUL D · NUBER PAUL DOUGLAS
10 granted patents·1 pending application·250 citations·filing 1994–2002
89Inventor score
Top patents by PatentIndex Score
11 records- 0192US6614260B1System and method for dynamic modification of integrated circuit functionalityAGILENT TECHNOLOGIES INC·Filed 2000·Granted Sep 2, 2003·68 cites·27 claims
- 0285US6405358B1Method for estimating and displaying wiring congestionAGILENT TECHNOLOGIES INC·Filed 1999·Granted Jun 11, 2002·131 cites·32 claims
- 0361US6832362B2Process and system for repeater insertion in an IC designAGILENT TECHNOLOGIES INC·Filed 2002·Granted Dec 14, 2004·9 cites·26 claims
- 0451US6653858B2Bypass capacitance localizationAGILENT TECHNOLOGIES INC·Filed 2001·Granted Nov 25, 2003·3 cites·14 claims
- 0550US6181182B1Circuit and method for a high gain, low input capacitance clock bufferAGILENT TECHNOLOGIES INC·Filed 1999·Granted Jan 30, 2001·12 cites·7 claims
- 0649US5426770ASystem for automatically determining the logical function of a circuitHEWLETT PACKARD CO·Filed 1994·Granted Jun 20, 1995·22 cites·9 claims
- 0743US6775116B2Method and apparatus for preventing buffers from being damaged by electrical charges collected on lines connected to the buffersAGILENT TECHNOLOGIES INC·Filed 2001·Granted Aug 10, 2004·2 cites·19 claims
- 0842US6734473B1Method of integrated circuit construction with port alignment and timing signal buffering within a common areaAGILENT TECHNOLOGIES INC·Filed 2000·Granted May 11, 2004·1 cites·13 claims
- 0938US2002129326A1Method for inserting repeaters in hierarchical chip designFiled 2001·Application pending·0 cites
- 1029US6894535B2Method and apparatus for ensuring signal integrity in a latch arrayAGILENT TECHNOLOGIES INC·Filed 2001·Granted May 17, 2005·0 cites·14 claims
- 1129US6118169AMethod for increasing power supply bypassing while decreasing chip layer density variationsAGILENT TECHNOLOGIES INC·Filed 1998·Granted Sep 12, 2000·2 cites·4 claims
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