Inventor · disambiguated record
Gary Lippert
Also filed as: LIPPERT GARY · LIPPERT GARY M · LIPPERT GARY MICHAEL
14 granted patents·394 citations·filing 1997–2013
93Inventor score
Top patents by PatentIndex Score
14 records- 0192US7340700B2Method for abstraction of manufacturing test access and control ports to support automated RTL manufacturing test insertion flow for reusable modulesLSI LOGIC CORP·Filed 2005·Granted Mar 4, 2008·39 cites·19 claims
- 0287US8095734B2Managing cache line allocations for multiple issue processorsLIPPERT GARY·Filed 2009·Granted Jan 10, 2012·26 cites·20 claims
- 0381US7157948B2Method and apparatus for calibrating a delay lineLSI LOGIC CORP·Filed 2004·Granted Jan 2, 2007·32 cites·22 claims
- 0480US6314491B1Peer-to-peer cache moves in a multiprocessor data processing systemIBM·Filed 1999·Granted Nov 6, 2001·95 cites·22 claims
- 0572US6557084B2Apparatus and method to improve performance of reads from and writes to shared memory locationsIBM·Filed 1999·Granted Apr 29, 2003·65 cites·27 claims
- 0665US6823431B2Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiencyIBM·Filed 2001·Granted Nov 23, 2004·9 cites·6 claims
- 0765US6065098AMethod for maintaining multi-level cache coherency in a processor with non-inclusive caches and processor implementing the sameIBM·Filed 1997·Granted May 16, 2000·46 cites·13 claims
- 0858US7496861B2Method for generalizing design attributes in a design capture environmentLSI CORP·Filed 2005·Granted Feb 24, 2009·1 cites·20 claims
- 0958US6871267B2Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiencyIBM·Filed 2001·Granted Mar 22, 2005·5 cites·20 claims
- 1058US6351791B1Circuit arrangement and method of maintaining cache coherence utilizing snoop response collection logic that disregards extraneous retry responsesIBM·Filed 1998·Granted Feb 26, 2002·35 cites·39 claims
- 1153US6467032B1Controlled reissue delay of memory requests to reduce shared memory address contentionIBM·Filed 1999·Granted Oct 15, 2002·26 cites·28 claims
- 1249US9235521B2Cache system for managing various cache line conditionsLSI CORP·Filed 2013·Granted Jan 12, 2016·0 cites·20 claims
- 1347US6260117B1Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiencyIBM·Filed 1998·Granted Jul 10, 2001·15 cites·10 claims
- 1439US8924779B2Proxy responder for handling anomalies in a hardware systemNATION GEORGE WAYNE·Filed 2012·Granted Dec 30, 2014·0 cites·23 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →