Inventor · disambiguated record
Bartholomew Blaner
Also filed as: BLANER BARTHOLOMEW
106 granted patents·4 pending applications·1,946 citations·filing 1987–2022
99Inventor score
Top patents by PatentIndex Score
110 records- 0197US9252805B1Parallel huffman decoderIBM·Filed 2015·Granted Feb 2, 2016·21 cites·20 claims
- 0295US10761995B2Integrated circuit and data processing system having a configurable cache directory for an acceleratorIBM·Filed 2019·Granted Sep 1, 2020·11 cites·20 claims
- 0393US9940191B2Concurrent error detection in a ternary content-addressable memory (TCAM) deviceIBM·Filed 2015·Granted Apr 10, 2018·10 cites·19 claims
- 0493US9584156B1Creating a dynamic Huffman tableIBM·Filed 2015·Granted Feb 28, 2017·12 cites·20 claims
- 0592US10552313B2Updating cache using two bloom filtersIBM·Filed 2018·Granted Feb 4, 2020·8 cites·1 claims
- 0691US9891912B2Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elementsIBM·Filed 2014·Granted Feb 13, 2018·11 cites·14 claims
- 0790US5355460AIn-memory preprocessor for compounding a sequence of instructions for parallel computer system executionIBM·Filed 1993·Granted Oct 11, 1994·127 cites·26 claims
- 0890US5287467APipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unitIBM·Filed 1991·Granted Feb 15, 1994·141 cites·19 claims
- 0990US5003462AApparatus and method for implementing precise interrupts on a pipelined processor with multiple functional units with separate address translation interrupt meansIBM·Filed 1988·Granted Mar 26, 1991·112 cites·13 claims
- 1089US8095777B2Structure for predictive decodingBLANER BARTHOLOMEW·Filed 2007·Granted Jan 10, 2012·22 cites·5 claims
- 1188US10216653B2Pre-transmission data reordering for a serial interfaceIBM·Filed 2017·Granted Feb 26, 2019·5 cites·19 claims
- 1288US8166279B2Method for predictive decoding of a load tagged pointer instructionBLANER BARTHOLOMEW·Filed 2007·Granted Apr 24, 2012·20 cites·3 claims
- 1388US5471628AMulti-function permutation switch for rotating and manipulating an order of bits of an input data byte in either cyclic or non-cyclic modeIBM·Filed 1992·Granted Nov 28, 1995·132 cites·11 claims
- 1487US9934030B2Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elementsIBM·Filed 2015·Granted Apr 3, 2018·4 cites·13 claims
- 1587US5214763ADigital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanismIBM·Filed 1990·Granted May 25, 1993·116 cites·10 claims
- 1685US7519793B2Facilitating inter-DSP data communicationsIBM·Filed 2007·Granted Apr 14, 2009·12 cites·18 claims
- 1785US5659722AMultiple condition code branching system in a multi-processor environmentIBM·Filed 1994·Granted Aug 19, 1997·110 cites·10 claims
- 1884US9417846B1Techniques for improving random number generation securityIBM·Filed 2015·Granted Aug 16, 2016·4 cites·8 claims
- 1981US9740629B2Tracking memory accesses when invalidating effective address to real address translationsIBM·Filed 2014·Granted Aug 22, 2017·5 cites·9 claims
- 2080US5051940AData dependency collapsing hardware apparatusIBM·Filed 1990·Granted Sep 24, 1991·84 cites·24 claims
- 2179US9208091B2Coherent attached processor proxy having hybrid directoryIBM·Filed 2013·Granted Dec 8, 2015·4 cites·14 claims
- 2279US5732234ASystem for obtaining parallel execution of existing instructions in a particulr data processing configuration by compounding rules based on instruction categoriesIBM·Filed 1996·Granted Mar 24, 1998·77 cites·9 claims
- 2378US9606861B2Concurrent error detection in a ternary content-addressable memory (TCAM) deviceIBM·Filed 2015·Granted Mar 28, 2017·4 cites·18 claims
- 2478US8938587B2Data recovery for coherent attached processor proxyIBM·Filed 2013·Granted Jan 20, 2015·4 cites·18 claims
- 2578US7849293B2Method and structure for low latency load-tagged pointer instruction for computer microarchitechtureIBM·Filed 2008·Granted Dec 7, 2010·8 cites·36 claims
- 2677US11113204B2Translation invalidation in a translation cache serving an acceleratorIBM·Filed 2019·Granted Sep 7, 2021·1 cites·20 claims
- 2777US10698812B2Updating cache using two bloom filtersIBM·Filed 2019·Granted Jun 30, 2020·1 cites·18 claims
- 2877US10394711B2Managing lowest point of coherency (LPC) memory using a service layer adapterIBM·Filed 2016·Granted Aug 27, 2019·2 cites·20 claims
- 2977US10078513B2Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elementsIBM·Filed 2017·Granted Sep 18, 2018·1 cites·16 claims
- 3077US5590348AStatus predictor for combined shifter-rotate/merge unitIBM·Filed 1992·Granted Dec 31, 1996·71 cites·25 claims
- 3176US5502826ASystem and method for obtaining parallel existing instructions in a particular data processing configuration by compounding instructionsIBM·Filed 1994·Granted Mar 26, 1996·59 cites·8 claims
- 3276US5303356ASystem for issuing instructions for parallel execution subsequent to branch into a group of member instructions with compoundability in dictation tagIBM·Filed 1991·Granted Apr 12, 1994·72 cites·13 claims
- 3376US4862461APacket switch network protocolIBM·Filed 1987·Granted Aug 29, 1989·48 cites·3 claims
- 3475US9628109B1Operation of a multi-slice processor implementing priority encoding of data pattern matchesIBM·Filed 2016·Granted Apr 18, 2017·3 cites·20 claims
- 3575US5504932ASystem for executing scalar instructions in parallel based on control bits appended by compounding decoderIBM·Filed 1995·Granted Apr 2, 1996·74 cites·13 claims
- 3674US9448846B2Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration enginesBASS BRIAN MITCHELL·Filed 2011·Granted Sep 20, 2016·3 cites·13 claims
- 3774US5459844APredecode instruction compoundingIBM·Filed 1994·Granted Oct 17, 1995·54 cites·11 claims
- 3874US5423011AApparatus for initializing branch prediction informationIBM·Filed 1992·Granted Jun 6, 1995·60 cites·11 claims
- 3974US5295249ACompounding preprocessor for cache for identifying multiple instructions which may be executed in parallelIBM·Filed 1991·Granted Mar 15, 1994·52 cites·26 claims
- 4072US9069674B2Coherent proxy for attached processorIBM·Filed 2012·Granted Jun 30, 2015·2 cites·20 claims
- 4172US7325122B2Facilitating inter-DSP data communicationsIBM·Filed 2004·Granted Jan 29, 2008·14 cites·9 claims
- 4271US5197135AMemory management for scalable compound instruction set machines with in-memory compoundingIBM·Filed 1990·Granted Mar 23, 1993·55 cites·15 claims
- 4370US10374628B2In-place data compression with small working memoryIBM·Filed 2017·Granted Aug 6, 2019·1 cites·20 claims
- 4468US5446850ACross-cache-line compounding algorithm for scism processorsIBM·Filed 1994·Granted Aug 29, 1995·42 cites·5 claims
- 4568US5386531AComputer system accelerator for multi-word cross-boundary storage accessIBM·Filed 1991·Granted Jan 31, 1995·52 cites·23 claims
- 4667US10346164B2Memory move instruction sequence targeting an accelerator switchboardIBM·Filed 2016·Granted Jul 9, 2019·1 cites·23 claims
- 4767US9727483B2Tracking memory accesses when invalidating effective address to real address translationsIBM·Filed 2015·Granted Aug 8, 2017·1 cites·7 claims
- 4867US9575728B1Random number generation securityIBM·Filed 2016·Granted Feb 21, 2017·1 cites·12 claims
- 4966US10599569B2Maintaining consistency between address translations in a data processing systemIBM·Filed 2016·Granted Mar 24, 2020·1 cites·17 claims
- 5065US11030110B2Integrated circuit and data processing system supporting address aliasing in an acceleratorIBM·Filed 2019·Granted Jun 8, 2021·0 cites·20 claims
Showing the top 50 of 110 patent records by PatentIndex Score.
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