Inventor · disambiguated record
Alfred Koelbl
Also filed as: KOELBL ALFRED
13 granted patents·1 pending application·75 citations·filing 2005–2022
91Inventor score
Technology areasG06F
Top patents by PatentIndex Score
14 records- 0188US7523423B1Method and apparatus for production of data-flow-graphs by symbolic simulationSYNOPSYS INC·Filed 2005·Granted Apr 21, 2009·15 cites·47 claims
- 0286US7260800B1Method and apparatus for initial state extractionSYNOPSYS INC·Filed 2005·Granted Aug 21, 2007·12 cites·19 claims
- 0385US7386820B1Method and apparatus for formally checking equivalence using equivalence relationshipsSYNOPSYS INC·Filed 2005·Granted Jun 10, 2008·12 cites·20 claims
- 0478US7509599B1Method and apparatus for performing formal verification using data-flow graphsSYNOPSYS INC·Filed 2005·Granted Mar 24, 2009·6 cites·29 claims
- 0578US7389479B2Formally proving the functional equivalence of pipelined designs containing memoriesSYNOPSYS INC·Filed 2006·Granted Jun 17, 2008·8 cites·20 claims
- 0677US8079000B2Method and apparatus for performing formal verification using data-flow graphsKOELBL ALFRED·Filed 2008·Granted Dec 13, 2011·6 cites·24 claims
- 0777US7836414B2Formally proving the functional equivalence of pipelined designs containing memoriesSYNOPSYS INC·Filed 2008·Granted Nov 16, 2010·7 cites·20 claims
- 0876US7509604B1Method and apparatus for formally comparing stream-based designsSYNOPSYS INC·Filed 2005·Granted Mar 24, 2009·5 cites·11 claims
- 0972US8001500B2Method and apparatus for formally checking equivalence using equivalence relationshipsSYNOPSYS INC·Filed 2008·Granted Aug 16, 2011·4 cites·30 claims
- 1051US8589836B2Formally checking equivalence using equivalence relationshipsKOELBL ALFRED·Filed 2008·Granted Nov 19, 2013·0 cites·21 claims
- 1149US10592624B2Efficient mechanism of fault qualification using formal verificationSYNOPSYS INC·Filed 2018·Granted Mar 17, 2020·0 cites·20 claims
- 1247US11556676B2Scalable formal security verification of circuit designsSYNOPSYS INC·Filed 2020·Granted Jan 17, 2023·0 cites·20 claims
- 1344US2023177244A1Creation of reduced formal model for scalable system-on-chip (soc) level connectivity verificationSYNOPSYS INC·Filed 2022·Application pending·0 cites
- 1441US8201119B2Formal equivalence checking between two models of a circuit design using checkpointsKOELBL ALFRED·Filed 2010·Granted Jun 12, 2012·0 cites·21 claims
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