Inventor · disambiguated record
Ruchir Puri
Also filed as: PURI RUCHIR
73 granted patents·9 pending applications·750 citations·filing 1994–2023
99Inventor score
Top patents by PatentIndex Score
82 records- 0198US11068797B2Automatic correction of indirect bias in machine learning modelsIBM·Filed 2018·Granted Jul 20, 2021·115 cites·20 claims
- 0294US8839162B2Specifying circuit level connectivity during circuit design synthesisAMUNDSON MICHAEL D·Filed 2010·Granted Sep 16, 2014·59 cites·25 claims
- 0393US8271920B2Converged large block and structured synthesis for high performance microprocessor designsCHO MINSIK·Filed 2010·Granted Sep 18, 2012·34 cites·22 claims
- 0492US10572569B2System, Method, and recording medium for mirroring matrices for batched Cholesky decomposition on a graphic processing unitIBM·Filed 2019·Granted Feb 25, 2020·5 cites·3 claims
- 0592US9984041B2System, method, and recording medium for mirroring matrices for batched cholesky decomposition on a graphic processing unitIBM·Filed 2016·Granted May 29, 2018·6 cites·19 claims
- 0692US7225421B2Clock tree distribution generation by determining allowed placement regions for clocked elementsIBM·Filed 2005·Granted May 29, 2007·38 cites·24 claims
- 0791US10423695B2System, method, and recording medium for mirroring matrices for batched Cholesky decomposition on a graphic processing unitIBM·Filed 2018·Granted Sep 24, 2019·5 cites·20 claims
- 0891US9606934B2Matrix ordering for cache efficiency in performing large sparse matrix operationsIBM·Filed 2015·Granted Mar 28, 2017·8 cites·21 claims
- 0990US7448014B2Design stage mitigation of interconnect variabilityIBM·Filed 2006·Granted Nov 4, 2008·20 cites·7 claims
- 1089US8495552B1Structured latch and local-clock-buffer planningCHO MINSIK·Filed 2012·Granted Jul 23, 2013·13 cites·15 claims
- 1189US7913202B2Wafer level I/O test, repair and/or customization enabled by I/O layerIBM·Filed 2007·Granted Mar 22, 2011·22 cites·18 claims
- 1289US7521950B2Wafer level I/O test and repair enabled by I/O layerIBM·Filed 2005·Granted Apr 21, 2009·21 cites·5 claims
- 1388US11036829B2System, method, and recording medium for mirroring matrices for batched Cholesky decomposition on a graphic processing unitIBM·Filed 2019·Granted Jun 15, 2021·3 cites·4 claims
- 1488US8527920B1Automated synthesis of high-performance two operand binary parallel prefix adderIBM·Filed 2013·Granted Sep 3, 2013·15 cites·24 claims
- 1587US11790035B2System, method, and recording medium for mirroring matrices for batched cholesky decomposition on a graphic processing unitIBM·Filed 2021·Granted Oct 17, 2023·1 cites·5 claims
- 1687US10373057B2Concept analysis operations utilizing acceleratorsIBM·Filed 2015·Granted Aug 6, 2019·4 cites·19 claims
- 1787US7119578B2Single supply level converterIBM·Filed 2003·Granted Oct 10, 2006·27 cites·12 claims
- 1886US9824756B2Mapping a lookup table to prefabricated TCAMSGLOBALFOUNDRIES INC·Filed 2013·Granted Nov 21, 2017·10 cites·14 claims
- 1986US8261226B1Network flow based module bottom surface metal pin assignmentBECKER WIREN DALE·Filed 2011·Granted Sep 4, 2012·13 cites·25 claims
- 2085US10685002B2Radix sort acceleration using custom asicIBM·Filed 2017·Granted Jun 16, 2020·3 cites·20 claims
- 2185US8010926B2Clock power minimization with regular physical placement of clock repeater componentsIBM·Filed 2008·Granted Aug 30, 2011·15 cites·17 claims
- 2284US5469367AMethodology and apparatus for modular partitioning for the machine design of asynchronous circuitsUNIV TECHNOLOGIES INT·Filed 1994·Granted Nov 21, 1995·107 cites·19 claims
- 2383US7336100B2Single supply level converterIBM·Filed 2006·Granted Feb 26, 2008·10 cites·19 claims
- 2482US12086207B2Mirroring matrices for batched cholesky decomposition on a graphic processing unitIBM·Filed 2023·Granted Sep 10, 2024·0 cites·3 claims
- 2582US8516412B2Soft hierarchy-based physical synthesis for large-scale, high-performance circuitsCHO MINSIK·Filed 2011·Granted Aug 20, 2013·8 cites·23 claims
- 2682US7480883B2Multiple voltage integrated circuit and design method thereforIBM·Filed 2006·Granted Jan 20, 2009·9 cites·8 claims
- 2780US9928261B2Radix sort acceleration using custom ASICIBM·Filed 2014·Granted Mar 27, 2018·4 cites·11 claims
- 2880US8104014B2Regular local clock buffer placement and latch clustering by iterative optimizationPURI RUCHIR·Filed 2008·Granted Jan 24, 2012·14 cites·20 claims
- 2980US7111266B2Multiple voltage integrated circuit and design method thereforIBM·Filed 2003·Granted Sep 19, 2006·23 cites·22 claims
- 3078US7500207B2Influence-based circuit designIBM·Filed 2006·Granted Mar 3, 2009·9 cites·20 claims
- 3177US10108670B2Parallel quicksortIBM·Filed 2015·Granted Oct 23, 2018·2 cites·20 claims
- 3275US10740232B2System, method and computer program product for accelerating iterative graph algorithms by memory layout optimizationIBM·Filed 2018·Granted Aug 11, 2020·1 cites·20 claims
- 3375US8365114B2Logic modification synthesisIBM·Filed 2010·Granted Jan 29, 2013·5 cites·6 claims
- 3475US7402854B2Three-dimensional cascaded power distribution in a semiconductor deviceIBM·Filed 2006·Granted Jul 22, 2008·5 cites·1 claims
- 3574US10671611B2Parallel quicksortIBM·Filed 2018·Granted Jun 2, 2020·1 cites·20 claims
- 3673US10831738B2Parallelized in-place radix sortingIBM·Filed 2017·Granted Nov 10, 2020·1 cites·20 claims
- 3773US6601223B1System and method for fast interconnect delay estimation through iterative refinementIBM·Filed 2000·Granted Jul 29, 2003·18 cites·20 claims
- 3872US10209913B2System, method and computer program product for accelerating iterative graph algorithms by memory layout optimizationIBM·Filed 2017·Granted Feb 19, 2019·1 cites·20 claims
- 3971US11507787B2Model agnostic contrastive explanations for structured dataIBM·Filed 2018·Granted Nov 22, 2022·2 cites·22 claims
- 4071US10310812B2Matrix ordering for cache efficiency in performing large sparse matrix operationsIBM·Filed 2017·Granted Jun 4, 2019·1 cites·20 claims
- 4171US7089510B2Method and program product of level converter optimizationIBM·Filed 2003·Granted Aug 8, 2006·15 cites·38 claims
- 4271US6724225B2Logic circuit for true and complement signal generatorIBM·Filed 2001·Granted Apr 20, 2004·15 cites·12 claims
- 4371US2023229943A1Post-hoc improvement of instance-level and group-level prediction metricsIBM·Filed 2023·Application pending·0 cites
- 4470US8566761B2Network flow based datapath bit slicingXIANG HUA·Filed 2011·Granted Oct 22, 2013·3 cites·18 claims
- 4567US10963794B2Concept analysis operations utilizing acceleratorsIBM·Filed 2019·Granted Mar 30, 2021·0 cites·20 claims
- 4666US10037190B2Transformation on input operands to reduce hardware overhead for implementing additionIBM·Filed 2016·Granted Jul 31, 2018·1 cites·19 claims
- 4763US8117568B2Apparatus, method and computer program product for fast simulation of manufacturing effects during integrated circuit designXIANG HUA·Filed 2008·Granted Feb 14, 2012·3 cites·22 claims
- 4862US8683398B1Automated synthesis of high-performance two operand binary parallel prefix adderIBM·Filed 2012·Granted Mar 25, 2014·1 cites·20 claims
- 4962US7552412B2Integrated circuit (IC) chip design method, program product and systemIBM·Filed 2005·Granted Jun 23, 2009·2 cites·26 claims
- 5061US8756541B2Relative ordering circuit synthesisCHO MINSIK·Filed 2012·Granted Jun 17, 2014·1 cites·23 claims
Showing the top 50 of 82 patent records by PatentIndex Score.
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